Commit c6c9dc87 authored by Farhana Aleen's avatar Farhana Aleen
Browse files

[AMDGPU] Supported ds_write_b128 generation. 

Summary: This is a follow-on patch of https://reviews.llvm.org/D44210

Author: FarhanaAleen

Reviewed By: msearles

Subscribers: llvm-commits, AMDGPU

Differential Revision: https://reviews.llvm.org/D44319

llvm-svn: 327726
parent c9977f38

llvm/lib/Target/AMDGPU/AMDGPUInstructions.td

+3 −0
Original line number Diff line number Diff line
@@ -383,6 +383,9 @@ def store_align8_local : Aligned8Bytes < 
  (ops node:$val, node:$ptr), (store_local node:$val, node:$ptr)

>;



def store_align16_local : Aligned16Bytes <

  (ops node:$val, node:$ptr), (store_local node:$val, node:$ptr)

>;



def load_flat          : FlatLoad <load>;

def az_extloadi8_flat  : FlatLoad <az_extloadi8>;

llvm/lib/Target/AMDGPU/DSInstructions.td

+2 −0
Original line number Diff line number Diff line
@@ -719,6 +719,8 @@ def : DS64Bit4ByteAlignedWritePat<DS_WRITE2_B32_gfx9, store_local>; 
let AddedComplexity = 100 in {



defm : DSWritePat_mc <DS_WRITE_B64, v2i32, "store_align8_local">;

defm : DSWritePat_mc <DS_WRITE_B128, v4i32, "store_align16_local">;



} // End AddedComplexity = 100

class DSAtomicRetPat<DS_Pseudo inst, ValueType vt, PatFrag frag> : GCNPat <

  (frag (DS1Addr1Offset i32:$ptr, i32:$offset), vt:$value),

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

+6 −6
Original line number Diff line number Diff line
@@ -5833,14 +5833,14 @@ SDValue SITargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const { 
      llvm_unreachable("unsupported private_element_size");

    }

  } else if (AS == AMDGPUASI.LOCAL_ADDRESS) {

    if (NumElements > 2)

      return SplitVectorStore(Op, DAG);



    if (NumElements == 2)

      return Op;

    // Use ds_write_b128 if possible.

    if (Subtarget->useDS128(EnableDS128) && Store->getAlignment() >= 16 &&

        VT.getStoreSize() == 16)

      return SDValue();



    // If properly aligned, if we split we might be able to use ds_write_b64.

    if (NumElements > 2)

      return SplitVectorStore(Op, DAG);

    return SDValue();

  } else {

    llvm_unreachable("unhandled address space");

  }

llvm/lib/Target/AMDGPU/SIInstrInfo.td

+5 −0
Original line number Diff line number Diff line
@@ -457,11 +457,16 @@ def store_glue_align8 : Aligned8Bytes < 
  (ops node:$value, node:$ptr), (store_glue node:$value, node:$ptr)

>;



def store_glue_align16 : Aligned16Bytes <

  (ops node:$value, node:$ptr), (store_glue node:$value, node:$ptr)

>;



def store_local_m0 : StoreFrag<store_glue>, LocalAddress;

def truncstorei8_local_m0 : StoreFrag<truncstorei8_glue>, LocalAddress;

def truncstorei16_local_m0 : StoreFrag<truncstorei16_glue>, LocalAddress;



def store_align8_local_m0 : StoreFrag<store_glue_align8>, LocalAddress;

def store_align16_local_m0 : StoreFrag<store_glue_align16>, LocalAddress;



def si_setcc_uniform : PatFrag <

  (ops node:$lhs, node:$rhs, node:$cond),

llvm/test/CodeGen/AMDGPU/load-local-f32.ll

+8 −3
Original line number Diff line number Diff line
@@ -2,7 +2,7 @@ 
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SICIVI,FUNC %s

; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefixes=EG,FUNC %s



; Testing for ds_read_128

; Testing for ds_read/write_128

; RUN: llc -march=amdgcn -mcpu=tahiti -amdgpu-ds128 < %s | FileCheck -check-prefixes=SI,FUNC %s

; RUN: llc -march=amdgcn -mcpu=tonga -amdgpu-ds128 < %s | FileCheck -check-prefixes=CIVI,FUNC %s

; RUN: llc -march=amdgcn -mcpu=gfx900 -amdgpu-ds128 < %s | FileCheck -check-prefixes=CIVI,FUNC %s
@@ -127,17 +127,22 @@ entry: 
  ret void

}



; Tests if ds_read_b128 gets generated for the 16 byte aligned load.

; Tests if ds_read/write_b128 gets generated for the 16 byte aligned load.

; FUNC-LABEL: {{^}}local_v4f32_to_128:



; SI-NOT: ds_read_b128

; SI-NOT: ds_write_b128



; CIVI: ds_read_b128

; CIVI: ds_write_b128



; EG: LDS_READ_RET

; EG: LDS_READ_RET

; EG: LDS_READ_RET

; EG: LDS_READ_RET

define amdgpu_kernel void @local_v4f32_to_128(<4 x float> addrspace(3)* %out, <4 x float> addrspace(3)* %in) {

  %ld = load <4 x float>, <4 x float> addrspace(3)* %in, align 16

  store <4 x float> %ld, <4 x float> addrspace(3)* %out

  store <4 x float> %ld, <4 x float> addrspace(3)* %out, align 16

  ret void

}