Commit c61881e7 authored by Tanya Lattner's avatar Tanya Lattner
Browse files

Merge 81814 from mainline. 

On x86-64, the 32-bit cmov doesn't actually clear the high 32-bit of
its result if the condition is false.

llvm-svn: 81977
parent c47a943d

llvm/lib/Target/X86/X86Instr64bit.td

+5 −3
Original line number Diff line number Diff line
@@ -363,13 +363,15 @@ def MOVZX64rm32 : I<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src), 
                    [(set GR64:$dst, (zextloadi64i32 addr:$src))]>;



// Any instruction that defines a 32-bit result leaves the high half of the

// register. Truncate can be lowered to EXTRACT_SUBREG, and CopyFromReg may

// be copying from a truncate, but any other 32-bit operation will zero-extend

// register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may

// be copying from a truncate. And x86's cmov doesn't do anything if the

// condition is false. But any other 32-bit operation will zero-extend

// up to 64 bits.

def def32 : PatLeaf<(i32 GR32:$src), [{

  return N->getOpcode() != ISD::TRUNCATE &&

         N->getOpcode() != TargetInstrInfo::EXTRACT_SUBREG &&

         N->getOpcode() != ISD::CopyFromReg;

         N->getOpcode() != ISD::CopyFromReg &&

         N->getOpcode() != X86ISD::CMOV;

}]>;



// In the case of a 32-bit def that is known to implicitly zero-extend,

llvm/test/CodeGen/X86/cmov-zext.ll

0 → 100644
+19 −0
Original line number Diff line number Diff line 
; RUN: llc < %s -march=x86-64 | FileCheck %s



; x86's 32-bit cmov doesn't clobber the high 32 bits of the destination

; if the condition is false. An explicit zero-extend (movl) is needed

; after the cmov.



; CHECK:      cmovne  %edi, %esi

; CHECK-NEXT: movl    %esi, %edi



declare void @bar(i64) nounwind



define void @foo(i64 %a, i64 %b, i1 %p) nounwind {

  %c = trunc i64 %a to i32

  %d = trunc i64 %b to i32

  %e = select i1 %p, i32 %c, i32 %d

  %f = zext i32 %e to i64

  call void @bar(i64 %f)

  ret void

}