Commit c5c1bb33 authored by Matt Arsenault's avatar Matt Arsenault
Browse files

GlobalISel: Lower G_WRITE_REGISTER

parent 2103e08b

llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h

+1 −1
Original line number Diff line number Diff line
@@ -265,7 +265,7 @@ public: 
  LegalizeResult lowerSADDO_SSUBO(MachineInstr &MI);

  LegalizeResult lowerBswap(MachineInstr &MI);

  LegalizeResult lowerBitreverse(MachineInstr &MI);

  LegalizeResult lowerReadRegister(MachineInstr &MI);

  LegalizeResult lowerReadWriteRegister(MachineInstr &MI);



private:

  MachineRegisterInfo &MRI;

llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp

+7 −0
Original line number Diff line number Diff line
@@ -1533,6 +1533,13 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID, 
        .addMetadata(cast<MDNode>(cast<MetadataAsValue>(Arg)->getMetadata()));

    return true;

  }

  case Intrinsic::write_register: {

    Value *Arg = CI.getArgOperand(0);

    MIRBuilder.buildInstr(TargetOpcode::G_WRITE_REGISTER)

      .addMetadata(cast<MDNode>(cast<MetadataAsValue>(Arg)->getMetadata()))

      .addUse(getOrCreateVReg(*CI.getArgOperand(1)));

    return true;

  }

  }

  return false;

}

llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

+20 −10
Original line number Diff line number Diff line
@@ -2478,7 +2478,8 @@ LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty) { 
  case G_BITREVERSE:

    return lowerBitreverse(MI);

  case G_READ_REGISTER:

    return lowerReadRegister(MI);

  case G_WRITE_REGISTER:

    return lowerReadWriteRegister(MI);

  }

}
@@ -4774,20 +4775,29 @@ LegalizerHelper::lowerBitreverse(MachineInstr &MI) { 
}



LegalizerHelper::LegalizeResult

LegalizerHelper::lowerReadRegister(MachineInstr &MI) {

  Register Dst = MI.getOperand(0).getReg();

  const LLT Ty = MRI.getType(Dst);

  const MDString *RegStr = cast<MDString>(

    cast<MDNode>(MI.getOperand(1).getMetadata())->getOperand(0));



LegalizerHelper::lowerReadWriteRegister(MachineInstr &MI) {

  MachineFunction &MF = MIRBuilder.getMF();

  const TargetSubtargetInfo &STI = MF.getSubtarget();

  const TargetLowering *TLI = STI.getTargetLowering();

  Register Reg = TLI->getRegisterByName(RegStr->getString().data(), Ty, MF);

  if (!Reg.isValid())



  bool IsRead = MI.getOpcode() == TargetOpcode::G_READ_REGISTER;

  int NameOpIdx = IsRead ? 1 : 0;

  int ValRegIndex = IsRead ? 0 : 1;



  Register ValReg = MI.getOperand(ValRegIndex).getReg();

  const LLT Ty = MRI.getType(ValReg);

  const MDString *RegStr = cast<MDString>(

    cast<MDNode>(MI.getOperand(NameOpIdx).getMetadata())->getOperand(0));



  Register PhysReg = TLI->getRegisterByName(RegStr->getString().data(), Ty, MF);

  if (!PhysReg.isValid())

    return UnableToLegalize;



  MIRBuilder.buildCopy(Dst, Reg);

  if (IsRead)

    MIRBuilder.buildCopy(ValReg, PhysReg);

  else

    MIRBuilder.buildCopy(PhysReg, ValReg);



  MI.eraseFromParent();

  return Legalized;

}

llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll

+1 −1
Original line number Diff line number Diff line
@@ -85,7 +85,7 @@ define i64 @atomic_ops(i64* %addr) { 
; Make sure we don't mess up metadata arguments.

declare void @llvm.write_register.i64(metadata, i64)



; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to translate instruction: call: ' call void @llvm.write_register.i64(metadata !0, i64 0)' (in function: test_write_register_intrin)

; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: G_WRITE_REGISTER !0, %0:_(s64) (in function: test_write_register_intrin)

; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for test_write_register_intrin

; FALLBACK-WITH-REPORT-LABEL: test_write_register_intrin:

define void @test_write_register_intrin() {

llvm/test/CodeGen/AMDGPU/GlobalISel/write_register.ll

0 → 100644
+2 −0
Original line number Diff line number Diff line 
; Runs original SDAG test with -global-isel

; RUN: llc -global-isel -march=amdgcn -mcpu=bonaire -enable-misched=0 -verify-machineinstrs < %S/../write_register.ll | FileCheck -enable-var-scope %S/../write_register.ll