Commit c4c93b74 authored by Matt Arsenault's avatar Matt Arsenault
Browse files

Merging rr308903: 

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r308903 | arsenm | 2017-07-24 11:06:15 -0700 (Mon, 24 Jul 2017) | 5 lines

AMDGPU: Fix allocating pseudo-registers

There's no need for these to be part of a class since
they are immediately replaced. New unreachable hit in
existing tests.'
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llvm-svn: 309157
parent 91174ebd

llvm/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp

+5 −0
Original line number Diff line number Diff line
@@ -297,6 +297,11 @@ void AMDGPUInstPrinter::printRegOperand(unsigned RegNo, raw_ostream &O, 
  case AMDGPU::FLAT_SCR_HI:

    O << "flat_scratch_hi";

    return;

  case AMDGPU::FP_REG:

  case AMDGPU::SP_REG:

  case AMDGPU::SCRATCH_WAVE_OFFSET_REG:

  case AMDGPU::PRIVATE_RSRC_REG:

    llvm_unreachable("pseudo-register should not ever be emitted");

  default:

    break;

  }

llvm/lib/Target/AMDGPU/SIRegisterInfo.td

+1 −2
Original line number Diff line number Diff line
@@ -274,8 +274,7 @@ def VGPR_512 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7, 
def SReg_32_XM0_XEXEC : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,

  (add SGPR_32, VCC_LO, VCC_HI, FLAT_SCR_LO, FLAT_SCR_HI,

   TTMP_32, TMA_LO, TMA_HI, TBA_LO, TBA_HI, SRC_SHARED_BASE, SRC_SHARED_LIMIT,

   SRC_PRIVATE_BASE, SRC_PRIVATE_LIMIT,

   FP_REG, SP_REG, SCRATCH_WAVE_OFFSET_REG)> {

   SRC_PRIVATE_BASE, SRC_PRIVATE_LIMIT)> {

  let AllocationPriority = 7;

}