Commit c499fcb1 authored by Tom Stellard's avatar Tom Stellard
Browse files

Merging r205630: 

------------------------------------------------------------------------
r205630 | hfinkel | 2014-04-04 11:15:57 -0400 (Fri, 04 Apr 2014) | 6 lines

[PowerPC] Add a full condition code register to make the "cc" clobber work

gcc inline asm supports specifying "cc" as a clobber of all condition
registers. Add just enough modeling of the full register to make this work.
Fixed PR19326.

------------------------------------------------------------------------

llvm-svn: 205908
parent 3bf56a8a

llvm/lib/Target/PowerPC/PPCRegisterInfo.td

+12 −0
Original line number Diff line number Diff line
@@ -144,6 +144,13 @@ def CR6 : CR<6, "cr6", [CR6LT, CR6GT, CR6EQ, CR6UN]>, DwarfRegNum<[74, 74]>; 
def CR7 : CR<7, "cr7", [CR7LT, CR7GT, CR7EQ, CR7UN]>, DwarfRegNum<[75, 75]>;

}



// The full condition-code register. This is not modeled fully, but defined

// here primarily, for compatibility with gcc, to allow the inline asm "cc"

// clobber specification to work.

def CC : PPCReg<"cc">, DwarfRegAlias<CR0> {

  let Aliases = [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7];

}



// Link register

def LR  : SPR<8, "lr">, DwarfRegNum<[-2, 65]>;

//let Aliases = [LR] in
@@ -234,3 +241,8 @@ def VRSAVERC : RegisterClass<"PPC", [i32], 32, (add VRSAVE)>; 
def CARRYRC : RegisterClass<"PPC", [i32], 32, (add CARRY)> {

  let CopyCost = -1;

}



def CCRC : RegisterClass<"PPC", [i32], 32, (add CC)> {

  let isAllocatable = 0;

}

llvm/test/CodeGen/PowerPC/cc.ll

0 → 100644
+70 −0
Original line number Diff line number Diff line 
; RUN: llc -mcpu=pwr7 < %s | FileCheck %s

target datalayout = "E-m:e-i64:64-n32:64"

target triple = "powerpc64-unknown-linux-gnu"



define i64 @test1(i64 %a, i64 %b) {

entry:

  %c = icmp eq i64 %a, %b

  br label %foo



foo:

  call { i64, i64 } asm sideeffect "sc", "={r0},={r3},{r0},~{cr0},~{cr1},~{cr2},~{cr3},~{cr4},~{cr5},~{cr6},~{cr7}" (i64 %a)

  br i1 %c, label %bar, label %end



bar:

  ret i64 %b



end:

  ret i64 %a



; CHECK-LABEL: @test1

; CHECK: mfcr [[REG1:[0-9]+]]

; CHECK-DAG: cmpld

; CHECK-DAG: mfocrf [[REG2:[0-9]+]],

; CHECK-DAG: stw [[REG1]], 8(1)

; CHECK-DAG: stw [[REG2]], -4(1)



; CHECK: sc

; CHECK: lwz [[REG3:[0-9]+]], -4(1)

; CHECK: mtocrf 128, [[REG3]]



; CHECK: lwz [[REG4:[0-9]+]], 8(1)

; CHECK-DAG: mtocrf 32, [[REG4]]

; CHECK-DAG: mtocrf 16, [[REG4]]

; CHECK-DAG: mtocrf 8, [[REG4]]

; CHECK: blr

}



define i64 @test2(i64 %a, i64 %b) {

entry:

  %c = icmp eq i64 %a, %b

  br label %foo



foo:

  call { i64, i64 } asm sideeffect "sc", "={r0},={r3},{r0},~{cc}" (i64 %a)

  br i1 %c, label %bar, label %end



bar:

  ret i64 %b



end:

  ret i64 %a



; CHECK-LABEL: @test2

; CHECK: mfcr [[REG1:[0-9]+]]

; CHECK-DAG: cmpld

; CHECK-DAG: mfocrf [[REG2:[0-9]+]],

; CHECK-DAG: stw [[REG1]], 8(1)

; CHECK-DAG: stw [[REG2]], -4(1)



; CHECK: sc

; CHECK: lwz [[REG3:[0-9]+]], -4(1)

; CHECK: mtocrf 128, [[REG3]]



; CHECK: lwz [[REG4:[0-9]+]], 8(1)

; CHECK-DAG: mtocrf 32, [[REG4]]

; CHECK-DAG: mtocrf 16, [[REG4]]

; CHECK-DAG: mtocrf 8, [[REG4]]

; CHECK: blr

}