Commit c201f241 authored by Dylan McKay's avatar Dylan McKay
Browse files

Merging r314897: 

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r314897 | dylanmckay | 2017-10-04 23:36:07 +1300 (Wed, 04 Oct 2017) | 3 lines

[AVR] Factor out mayLoad in tablegen patterns

Patch by Gergo Erdi.
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llvm-svn: 315835
parent fb12e5f4

llvm/lib/Target/AVR/AVRInstrInfo.td

+2 −2
Original line number Diff line number Diff line
@@ -1417,6 +1417,7 @@ def STDWPtrQRr : Pseudo<(outs), 
// Load program memory operations.

let canFoldAsLoad = 1,

isReMaterializable = 1,

mayLoad = 1,

hasSideEffects = 0 in

{

  let Defs = [R0],
@@ -1437,8 +1438,7 @@ hasSideEffects = 0 in 
               Requires<[HasLPMX]>;



  // Load program memory, while postincrementing the Z register.

  let mayLoad = 1,

  Defs = [R31R30] in

  let Defs = [R31R30] in

  {

    def LPMRdZPi : FLPMX<0,

                         1,