Commit bf41dc4e authored by Hans Wennborg's avatar Hans Wennborg
Browse files

Merging r243469: 

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r243469 | vkalintiris | 2015-07-28 12:57:25 -0700 (Tue, 28 Jul 2015) | 12 lines

[mips][FastISel] Fix generated code for IR's select instruction.

Summary:
Generate correct code for the select instruction by zero-extending
it's boolean/condition operand to GPR-width. This is necessary because
the conditional-move instructions operate on the whole register.

Reviewers: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11506
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llvm-svn: 243646
parent 4a08cec9

llvm/lib/Target/Mips/MipsFastISel.cpp

+8 −1
Original line number Diff line number Diff line
@@ -981,6 +981,13 @@ bool MipsFastISel::selectSelect(const Instruction *I) { 
  if (!Src1Reg || !Src2Reg || !CondReg)

    return false;



  unsigned ZExtCondReg = createResultReg(&Mips::GPR32RegClass);

  if (!ZExtCondReg)

    return false;



  if (!emitIntExt(MVT::i1, CondReg, MVT::i32, ZExtCondReg, true))

    return false;



  unsigned ResultReg = createResultReg(RC);

  unsigned TempReg = createResultReg(RC);
@@ -989,7 +996,7 @@ bool MipsFastISel::selectSelect(const Instruction *I) { 


  emitInst(TargetOpcode::COPY, TempReg).addReg(Src2Reg);

  emitInst(CondMovOpc, ResultReg)

    .addReg(Src1Reg).addReg(CondReg).addReg(TempReg);

    .addReg(Src1Reg).addReg(ZExtCondReg).addReg(TempReg);

  updateValueMap(I, ResultReg);

  return true;

}

llvm/test/CodeGen/Mips/Fast-ISel/sel1.ll

+12 −6
Original line number Diff line number Diff line
@@ -8,7 +8,8 @@ entry: 
  ; FIXME: The following instruction is redundant.

  ; CHECK:            xor     $[[T0:[0-9]+]], $4, $zero

  ; CHECK-NEXT:       sltu    $[[T1:[0-9]+]], $zero, $[[T0]]

  ; CHECK-NEXT:       movn    $6, $5, $[[T1]]

  ; CHECK-NEXT:       andi    $[[T2:[0-9]+]], $[[T1]], 1

  ; CHECK-NEXT:       movn    $6, $5, $[[T2]]

  ; CHECK:            move    $2, $6

  %cond = icmp ne i1 %j, 0

  %res = select i1 %cond, i1 %k, i1 %l
@@ -24,7 +25,8 @@ entry: 
  ; CHECK-DAG:        seb     $[[T1:[0-9]+]], $zero

  ; CHECK:            xor     $[[T2:[0-9]+]], $[[T0]], $[[T1]]

  ; CHECK-NEXT:       sltu    $[[T3:[0-9]+]], $zero, $[[T2]]

  ; CHECK-NEXT:       movn    $6, $5, $[[T3]]

  ; CHECK-NEXT:       andi    $[[T4:[0-9]+]], $[[T3]], 1

  ; CHECK-NEXT:       movn    $6, $5, $[[T4]]

  ; CHECK:            move    $2, $6

  %cond = icmp ne i8 %j, 0

  %res = select i1 %cond, i8 %k, i8 %l
@@ -40,7 +42,8 @@ entry: 
  ; CHECK-DAG:        seh     $[[T1:[0-9]+]], $zero

  ; CHECK:            xor     $[[T2:[0-9]+]], $[[T0]], $[[T1]]

  ; CHECK-NEXT:       sltu    $[[T3:[0-9]+]], $zero, $[[T2]]

  ; CHECK-NEXT:       movn    $6, $5, $[[T3]]

  ; CHECK-NEXT:       andi    $[[T4:[0-9]+]], $[[T3]], 1

  ; CHECK-NEXT:       movn    $6, $5, $[[T4]]

  ; CHECK:            move    $2, $6

  %cond = icmp ne i16 %j, 0

  %res = select i1 %cond, i16 %k, i16 %l
@@ -54,7 +57,8 @@ entry: 
  ; FIXME: The following instruction is redundant.

  ; CHECK:            xor     $[[T0:[0-9]+]], $4, $zero

  ; CHECK-NEXT:       sltu    $[[T1:[0-9]+]], $zero, $[[T0]]

  ; CHECK-NEXT:       movn    $6, $5, $[[T1]]

  ; CHECK-NEXT:       andi    $[[T2:[0-9]+]], $[[T1]], 1

  ; CHECK-NEXT:       movn    $6, $5, $[[T2]]

  ; CHECK:            move    $2, $6

  %cond = icmp ne i32 %j, 0

  %res = select i1 %cond, i32 %k, i32 %l
@@ -69,7 +73,8 @@ entry: 
  ; CHECK-DAG:        mtc1    $5, $f1

  ; CHECK-DAG:        xor     $[[T0:[0-9]+]], $4, $zero

  ; CHECK:            sltu    $[[T1:[0-9]+]], $zero, $[[T0]]

  ; CHECK:            movn.s  $f0, $f1, $[[T1]]

  ; CHECK-NEXT:       andi    $[[T2:[0-9]+]], $[[T1]], 1

  ; CHECK:            movn.s  $f0, $f1, $[[T2]]

  %cond = icmp ne i32 %j, 0

  %res = select i1 %cond, float %k, float %l

  ret float %res
@@ -84,7 +89,8 @@ entry: 
  ; CHECK-DAG:        ldc1    $f0, 16($sp)

  ; CHECK-DAG:        xor     $[[T0:[0-9]+]], $4, $zero

  ; CHECK:            sltu    $[[T1:[0-9]+]], $zero, $[[T0]]

  ; CHECK:            movn.d  $f0, $f2, $[[T1]]

  ; CHECK-NEXT:       andi    $[[T2:[0-9]+]], $[[T1]], 1

  ; CHECK:            movn.d  $f0, $f2, $[[T2]]

  %cond = icmp ne i32 %j, 0

  %res = select i1 %cond, double %k, double %l

  ret double %res