Commit bd5e4431 authored by Tom Stellard's avatar Tom Stellard
Browse files

Merging r268295: 

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r268295 | thomas.stellard | 2016-05-02 13:11:44 -0700 (Mon, 02 May 2016) | 7 lines

AMDGPU/SI: Use v_readfirstlane_b32 when restoring SGPRs spilled to
scratch

We were using v_readlane_b32 with the lane set to zero, but this won't
work if thread 0 is not active.

Differential Revision: http://reviews.llvm.org/D19745

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llvm-svn: 271771
parent 14cffe0b

llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp

+1 −2
Original line number Diff line number Diff line
@@ -410,9 +410,8 @@ void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI, 
                  .addImm(i * 4)                          // offset

                  .addMemOperand(MMO);

          BuildMI(*MBB, MI, DL,

                  TII->getMCOpcodeFromPseudo(AMDGPU::V_READLANE_B32), SubReg)

                  TII->get(AMDGPU::V_READFIRSTLANE_B32), SubReg)

                  .addReg(TmpReg, RegState::Kill)

                  .addImm(0)

                  .addReg(MI->getOperand(0).getReg(), RegState::ImplicitDefine);

        }

      }

llvm/test/CodeGen/AMDGPU/si-spill-sgpr-stack.ll

+6 −0
Original line number Diff line number Diff line
@@ -2,6 +2,12 @@ 


; Make sure this doesn't crash.

; CHECK: {{^}}test:

; Make sure we are handling hazards correctly.

; CHECK: buffer_load_dword [[VHI:v[0-9]+]], s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offset:16

; CHECK-NEXT: s_waitcnt vmcnt(0)

; CHECK-NEXT: v_readfirstlane_b32 s[[HI:[0-9]+]], [[VHI]]

; CHECK-NEXT: s_nop 4

; CHECK-NEXT: buffer_store_dword v0, s[0:[[HI]]{{\]}}, 0

; CHECK: s_endpgm

define void @test(i32 addrspace(1)* %out, i32 %in) {

  call void asm sideeffect "", "~{SGPR0_SGPR1_SGPR2_SGPR3_SGPR4_SGPR5_SGPR6_SGPR7}" ()