Unverified Commit bb9dced2 authored by David Spickett's avatar David Spickett Committed by GitHub
Browse files

[lldb][AArch64][Linux] Rename Is<ext>Enabled to Is<ext>Present (#70303) 

For most register sets, if it was enabled this meant you could use it,
it was present in the process. There was no present but turned off
state. So "enabled" made sense.

Then ZA came along (and soon to be ZT0) where ZA can be present in the
hardware when you have SME, but ZA itself can be made inactive. This
means that "IsZAEnabled()" doesn't mean is it active, it means do you
have SME. Which is very confusing when we actually want to know if ZA is
active.

So instead say "IsZAPresent", to make these checks more specific. For
things that can't be made inactive, present will imply "active" as
they're never inactive.
parent 8bc4462b

lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp

+10 −11
Original line number Diff line number Diff line
@@ -166,10 +166,10 @@ NativeRegisterContextLinux_arm64::NativeRegisterContextLinux_arm64( 
  m_tls_is_valid = false;



  // SME adds the tpidr2 register

  m_tls_size = GetRegisterInfo().IsSSVEEnabled() ? sizeof(m_tls_regs)

  m_tls_size = GetRegisterInfo().IsSSVEPresent() ? sizeof(m_tls_regs)

                                                 : sizeof(m_tls_regs.tpidr_reg);



  if (GetRegisterInfo().IsSVEEnabled() || GetRegisterInfo().IsSSVEEnabled())

  if (GetRegisterInfo().IsSVEPresent() || GetRegisterInfo().IsSSVEPresent())

    m_sve_state = SVEState::Unknown;

  else

    m_sve_state = SVEState::Disabled;
@@ -609,8 +609,7 @@ NativeRegisterContextLinux_arm64::CacheAllRegisters(uint32_t &cached_size) { 
  if (error.Fail())

    return error;



  // Here this means, does the system have ZA, not whether it is active.

  if (GetRegisterInfo().IsZAEnabled()) {

  if (GetRegisterInfo().IsZAPresent()) {

    error = ReadZAHeader();

    if (error.Fail())

      return error;
@@ -628,7 +627,7 @@ NativeRegisterContextLinux_arm64::CacheAllRegisters(uint32_t &cached_size) { 
  }



  // If SVE is enabled we need not copy FPR separately.

  if (GetRegisterInfo().IsSVEEnabled() || GetRegisterInfo().IsSSVEEnabled()) {

  if (GetRegisterInfo().IsSVEPresent() || GetRegisterInfo().IsSSVEPresent()) {

    // Store mode and register data.

    cached_size +=

        sizeof(RegisterSetType) + sizeof(m_sve_state) + GetSVEBufferSize();
@@ -640,7 +639,7 @@ NativeRegisterContextLinux_arm64::CacheAllRegisters(uint32_t &cached_size) { 
  if (error.Fail())

    return error;



  if (GetRegisterInfo().IsMTEEnabled()) {

  if (GetRegisterInfo().IsMTEPresent()) {

    cached_size += sizeof(RegisterSetType) + GetMTEControlSize();

    error = ReadMTEControl();

    if (error.Fail())
@@ -708,7 +707,7 @@ Status NativeRegisterContextLinux_arm64::ReadAllRegisterValues( 
  // constants and the functions vec_set_vector_length, sve_set_common and

  // za_set in the Linux Kernel.



  if ((m_sve_state != SVEState::Streaming) && GetRegisterInfo().IsZAEnabled()) {

  if ((m_sve_state != SVEState::Streaming) && GetRegisterInfo().IsZAPresent()) {

    // Use the header size not the buffer size, as we may be using the buffer

    // for fake data, which we do not want to write out.

    assert(m_za_header.size <= GetZABufferSize());
@@ -716,7 +715,7 @@ Status NativeRegisterContextLinux_arm64::ReadAllRegisterValues( 
                            m_za_header.size);

  }



  if (GetRegisterInfo().IsSVEEnabled() || GetRegisterInfo().IsSSVEEnabled()) {

  if (GetRegisterInfo().IsSVEPresent() || GetRegisterInfo().IsSSVEPresent()) {

    dst = AddRegisterSetType(dst, RegisterSetType::SVE);

    *(reinterpret_cast<SVEState *>(dst)) = m_sve_state;

    dst += sizeof(m_sve_state);
@@ -726,13 +725,13 @@ Status NativeRegisterContextLinux_arm64::ReadAllRegisterValues( 
                            GetFPRSize());

  }



  if ((m_sve_state == SVEState::Streaming) && GetRegisterInfo().IsZAEnabled()) {

  if ((m_sve_state == SVEState::Streaming) && GetRegisterInfo().IsZAPresent()) {

    assert(m_za_header.size <= GetZABufferSize());

    dst = AddSavedRegisters(dst, RegisterSetType::SME, GetZABuffer(),

                            m_za_header.size);

  }



  if (GetRegisterInfo().IsMTEEnabled()) {

  if (GetRegisterInfo().IsMTEPresent()) {

    dst = AddSavedRegisters(dst, RegisterSetType::MTE, GetMTEControl(),

                            GetMTEControlSize());

  }
@@ -1411,7 +1410,7 @@ std::vector<uint32_t> NativeRegisterContextLinux_arm64::GetExpeditedRegisters( 
    expedited_reg_nums.push_back(GetRegisterInfo().GetRegNumSVEVG());

  // SME, streaming vector length. This is used by the ZA register which is

  // present even when streaming mode is not enabled.

  if (GetRegisterInfo().IsSSVEEnabled())

  if (GetRegisterInfo().IsSSVEPresent())

    expedited_reg_nums.push_back(GetRegisterInfo().GetRegNumSMESVG());



  return expedited_reg_nums;

lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h

+6 −6
Original line number Diff line number Diff line
@@ -120,12 +120,12 @@ public: 
    return false;

  }



  bool IsSVEEnabled() const { return m_opt_regsets.AnySet(eRegsetMaskSVE); }

  bool IsSSVEEnabled() const { return m_opt_regsets.AnySet(eRegsetMaskSSVE); }

  bool IsZAEnabled() const { return m_opt_regsets.AnySet(eRegsetMaskZA); }

  bool IsPAuthEnabled() const { return m_opt_regsets.AnySet(eRegsetMaskPAuth); }

  bool IsMTEEnabled() const { return m_opt_regsets.AnySet(eRegsetMaskMTE); }

  bool IsTLSEnabled() const { return m_opt_regsets.AnySet(eRegsetMaskTLS); }

  bool IsSVEPresent() const { return m_opt_regsets.AnySet(eRegsetMaskSVE); }

  bool IsSSVEPresent() const { return m_opt_regsets.AnySet(eRegsetMaskSSVE); }

  bool IsZAPresent() const { return m_opt_regsets.AnySet(eRegsetMaskZA); }

  bool IsPAuthPresent() const { return m_opt_regsets.AnySet(eRegsetMaskPAuth); }

  bool IsMTEPresent() const { return m_opt_regsets.AnySet(eRegsetMaskMTE); }

  bool IsTLSPresent() const { return m_opt_regsets.AnySet(eRegsetMaskTLS); }



  bool IsSVEReg(unsigned reg) const;

  bool IsSVEZReg(unsigned reg) const;

lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.cpp

+6 −6
Original line number Diff line number Diff line
@@ -75,7 +75,7 @@ RegisterContextCorePOSIX_arm64::RegisterContextCorePOSIX_arm64( 
      m_register_info_up->GetTargetArchitecture().GetTriple();

  m_fpr_data = getRegset(notes, target_triple, FPR_Desc);



  if (m_register_info_up->IsSSVEEnabled()) {

  if (m_register_info_up->IsSSVEPresent()) {

    m_sve_data = getRegset(notes, target_triple, AARCH64_SSVE_Desc);

    lldb::offset_t flags_offset = 12;

    uint16_t flags = m_sve_data.GetU32(&flags_offset);
@@ -83,19 +83,19 @@ RegisterContextCorePOSIX_arm64::RegisterContextCorePOSIX_arm64( 
      m_sve_state = SVEState::Streaming;

  }



  if (m_sve_state != SVEState::Streaming && m_register_info_up->IsSVEEnabled())

  if (m_sve_state != SVEState::Streaming && m_register_info_up->IsSVEPresent())

    m_sve_data = getRegset(notes, target_triple, AARCH64_SVE_Desc);



  if (m_register_info_up->IsPAuthEnabled())

  if (m_register_info_up->IsPAuthPresent())

    m_pac_data = getRegset(notes, target_triple, AARCH64_PAC_Desc);



  if (m_register_info_up->IsTLSEnabled())

  if (m_register_info_up->IsTLSPresent())

    m_tls_data = getRegset(notes, target_triple, AARCH64_TLS_Desc);



  if (m_register_info_up->IsZAEnabled())

  if (m_register_info_up->IsZAPresent())

    m_za_data = getRegset(notes, target_triple, AARCH64_ZA_Desc);



  if (m_register_info_up->IsMTEEnabled())

  if (m_register_info_up->IsMTEPresent())

    m_mte_data = getRegset(notes, target_triple, AARCH64_MTE_Desc);



  ConfigureRegisterContext();