Unverified Commit b6ecdf0a authored by Ivan Kosarev's avatar Ivan Kosarev Committed by GitHub
Browse files

[AMDGPU] Segregate 16-bit fix-sgpr-copies tests. (#69353) 

The 16-bit instructions used in them are not available on the generic
target. This patches makes them run for GFX11.
parent bb826951

llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16.mir

0 → 100644
+58 −0
Original line number Diff line number Diff line 
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3

# RUN: llc -march=amdgcn -mcpu=gfx1100 -run-pass=si-fix-sgpr-copies -verify-machineinstrs -o - %s | FileCheck --check-prefix=GCN %s



---

name:            cmp_f16

body:             |

  bb.0.entry:

    ; GCN-LABEL: name: cmp_f16

    ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF

    ; GCN-NEXT: [[DEF1:%[0-9]+]]:sreg_32 = IMPLICIT_DEF

    ; GCN-NEXT: [[V_CVT_F16_U16_e64_:%[0-9]+]]:vgpr_32 = V_CVT_F16_U16_e64 [[DEF]], 0, 0, implicit $mode, implicit $exec

    ; GCN-NEXT: [[DEF2:%[0-9]+]]:sreg_32 = IMPLICIT_DEF

    ; GCN-NEXT: [[V_CMP_LT_F16_t16_e64_:%[0-9]+]]:sreg_32_xm0_xexec = nofpexcept V_CMP_LT_F16_t16_e64 0, [[V_CVT_F16_U16_e64_]], 0, [[DEF1]], 0, implicit $mode, implicit $exec

    ; GCN-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, -1, killed [[V_CMP_LT_F16_t16_e64_]], implicit $exec

    %0:vgpr_32 = IMPLICIT_DEF

    %1:sreg_32 = IMPLICIT_DEF

    %2:vgpr_32 = V_CVT_F16_U16_e64 %0:vgpr_32, 0, 0, implicit $mode, implicit $exec

    %3:sreg_32 = COPY %2:vgpr_32

    nofpexcept S_CMP_LT_F16 killed %3:sreg_32, %1:sreg_32, implicit-def $scc, implicit $mode

    %4:sreg_32_xm0_xexec = COPY $scc

    %5:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, -1, killed %4, implicit $exec

...



# Needs extra shift instruction to select hi 16 bits

---

name:            cvt_hi_f32_f16

body:             |

  bb.0:

    ; GCN-LABEL: name: cvt_hi_f32_f16

    ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF

    ; GCN-NEXT: [[V_CVT_F16_U16_e64_:%[0-9]+]]:vgpr_32 = V_CVT_F16_U16_e64 [[DEF]], 0, 0, implicit $mode, implicit $exec

    ; GCN-NEXT: [[DEF1:%[0-9]+]]:sreg_32 = IMPLICIT_DEF

    ; GCN-NEXT: [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 16, [[V_CVT_F16_U16_e64_]], implicit $exec

    ; GCN-NEXT: [[V_CVT_F32_F16_t16_e64_:%[0-9]+]]:vgpr_32 = V_CVT_F32_F16_t16_e64 0, [[V_LSHRREV_B32_e64_]], 0, 0, implicit $mode, implicit $exec

    %0:vgpr_32 = IMPLICIT_DEF

    %1:vgpr_32 = V_CVT_F16_U16_e64 %0:vgpr_32, 0, 0, implicit $mode, implicit $exec

    %2:sreg_32 = COPY %1:vgpr_32

    %3:sreg_32 = S_CVT_HI_F32_F16 %2:sreg_32, implicit $mode

...



---

name:            fmac_f16

body:             |

  bb.0:

    ; GCN-LABEL: name: fmac_f16

    ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF

    ; GCN-NEXT: [[DEF1:%[0-9]+]]:sreg_32 = IMPLICIT_DEF

    ; GCN-NEXT: [[DEF2:%[0-9]+]]:sreg_32 = IMPLICIT_DEF

    ; GCN-NEXT: [[V_CVT_F32_U32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_F32_U32_e64 [[DEF]], 0, 0, implicit $mode, implicit $exec

    ; GCN-NEXT: [[DEF3:%[0-9]+]]:sreg_32 = IMPLICIT_DEF

    ; GCN-NEXT: [[V_FMAC_F16_t16_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_FMAC_F16_t16_e64 0, killed [[DEF1]], 0, [[DEF2]], 0, [[V_CVT_F32_U32_e64_]], 0, 0, 0, implicit $mode, implicit $exec

    %0:vgpr_32 = IMPLICIT_DEF

    %1:sreg_32 = IMPLICIT_DEF

    %2:sreg_32 = IMPLICIT_DEF

    %3:vgpr_32 = V_CVT_F32_U32_e64 %0:vgpr_32, 0, 0, implicit $mode, implicit $exec

    %4:sreg_32 = COPY %3:vgpr_32

    %5:sreg_32 = nofpexcept S_FMAC_F16 killed %1:sreg_32, %2:sreg_32, %4:sreg_32, implicit $mode

...

llvm/test/CodeGen/AMDGPU/fix-sgpr-copies.mir

+0 −58
Original line number Diff line number Diff line
@@ -202,44 +202,6 @@ body: | 
    %5:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, -1, killed %4, implicit $exec

...



---

name:            cmp_f16

body:             |

  bb.0.entry:

    ; GCN-LABEL: name: cmp_f16

    ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF

    ; GCN-NEXT: [[DEF1:%[0-9]+]]:sreg_32 = IMPLICIT_DEF

    ; GCN-NEXT: [[V_CVT_F16_U16_e64_:%[0-9]+]]:vgpr_32 = V_CVT_F16_U16_e64 [[DEF]], 0, 0, implicit $mode, implicit $exec

    ; GCN-NEXT: [[DEF2:%[0-9]+]]:sreg_32 = IMPLICIT_DEF

    ; GCN-NEXT: [[V_CMP_LT_F16_t16_e64_:%[0-9]+]]:sreg_64_xexec = nofpexcept V_CMP_LT_F16_t16_e64 0, [[V_CVT_F16_U16_e64_]], 0, [[DEF1]], 0, implicit $mode, implicit $exec

    ; GCN-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, -1, killed [[V_CMP_LT_F16_t16_e64_]], implicit $exec

    %0:vgpr_32 = IMPLICIT_DEF

    %1:sreg_32 = IMPLICIT_DEF

    %2:vgpr_32 = V_CVT_F16_U16_e64 %0:vgpr_32, 0, 0, implicit $mode, implicit $exec

    %3:sreg_32 = COPY %2:vgpr_32

    nofpexcept S_CMP_LT_F16 killed %3:sreg_32, %1:sreg_32, implicit-def $scc, implicit $mode

    %4:sreg_64_xexec = COPY $scc

    %5:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, -1, killed %4, implicit $exec

...



# Needs extra shift instruction to select hi 16 bits

---

name:            cvt_hi_f32_f16

body:             |

  bb.0:



    ; GCN-LABEL: name: cvt_hi_f32_f16

    ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF

    ; GCN-NEXT: [[V_CVT_F16_U16_e64_:%[0-9]+]]:vgpr_32 = V_CVT_F16_U16_e64 [[DEF]], 0, 0, implicit $mode, implicit $exec

    ; GCN-NEXT: [[DEF1:%[0-9]+]]:sreg_32 = IMPLICIT_DEF

    ; GCN-NEXT: [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 16, [[V_CVT_F16_U16_e64_]], implicit $exec

    ; GCN-NEXT: [[V_CVT_F32_F16_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_F16_t16_e64 0, [[V_LSHRREV_B32_e64_]], 0, 0, implicit $mode, implicit $exec

    %0:vgpr_32 = IMPLICIT_DEF

    %1:vgpr_32 = V_CVT_F16_U16_e64 %0:vgpr_32, 0, 0, implicit $mode, implicit $exec

    %2:sreg_32 = COPY %1:vgpr_32

    %3:sreg_32 = S_CVT_HI_F32_F16 %2:sreg_32, implicit $mode

...



# Test to ensure that src2 of fmac is moved to vgpr

---

name:            fmac_f32
@@ -260,23 +222,3 @@ body: | 
    %4:sreg_32 = COPY %3:vgpr_32

    %5:sreg_32 = nofpexcept S_FMAC_F32 killed %4:sreg_32, %1:sreg_32, %2:sreg_32, implicit $mode

...
 


---

name:            fmac_f16

body:             |

  bb.0:

    ; GCN-LABEL: name: fmac_f16

    ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF

    ; GCN-NEXT: [[DEF1:%[0-9]+]]:sreg_32 = IMPLICIT_DEF

    ; GCN-NEXT: [[DEF2:%[0-9]+]]:sreg_32 = IMPLICIT_DEF

    ; GCN-NEXT: [[V_CVT_F32_U32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_F32_U32_e64 [[DEF]], 0, 0, implicit $mode, implicit $exec

    ; GCN-NEXT: [[DEF3:%[0-9]+]]:sreg_32 = IMPLICIT_DEF

    ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF2]]

    ; GCN-NEXT: %6:vgpr_32 = nofpexcept V_FMAC_F16_t16_e64 0, killed [[DEF1]], 0, [[COPY]], 0, [[V_CVT_F32_U32_e64_]], 0, 0, 0, implicit $mode, implicit $exec

    %0:vgpr_32 = IMPLICIT_DEF

    %1:sreg_32 = IMPLICIT_DEF

    %2:sreg_32 = IMPLICIT_DEF

    %3:vgpr_32 = V_CVT_F32_U32_e64 %0:vgpr_32, 0, 0, implicit $mode, implicit $exec

    %4:sreg_32 = COPY %3:vgpr_32

    %5:sreg_32 = nofpexcept S_FMAC_F16 killed %1:sreg_32, %2:sreg_32, %4:sreg_32, implicit $mode

...