Commit b6794b61 authored by Hans Wennborg's avatar Hans Wennborg
Browse files

Merging r276980: 

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r276980 | tstellar | 2016-07-28 07:30:43 -0700 (Thu, 28 Jul 2016) | 12 lines

AMDGPU/SI: Don't use reserved VGPRs for SGPR spilling

Summary:
We were using reserved VGPRs for SGPR spilling and this was causing
some programs with a workgroup size of 1024 to use more than 64
registers, which is illegal.

Reviewers: arsenm, mareko, nhaehnle

Subscribers: nhaehnle, arsenm, llvm-commits, kzhuravl

Differential Revision: https://reviews.llvm.org/D22032
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llvm-svn: 277084
parent 2ec706fe

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

+2 −1
Original line number Diff line number Diff line
@@ -738,7 +738,8 @@ unsigned SIInstrInfo::calculateLDSSpillAddress( 
    MachineBasicBlock::iterator Insert = Entry.front();

    DebugLoc DL = Insert->getDebugLoc();



    TIDReg = RI.findUnusedRegister(MF->getRegInfo(), &AMDGPU::VGPR_32RegClass);

    TIDReg = RI.findUnusedRegister(MF->getRegInfo(), &AMDGPU::VGPR_32RegClass,

                                   *MF);

    if (TIDReg == AMDGPU::NoRegister)

      return TIDReg;

llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp

+2 −1
Original line number Diff line number Diff line
@@ -203,7 +203,8 @@ SIMachineFunctionInfo::SpilledReg SIMachineFunctionInfo::getSpilledReg ( 
  Spill.Lane = Lane;



  if (!LaneVGPRs.count(LaneVGPRIdx)) {

    unsigned LaneVGPR = TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass);

    unsigned LaneVGPR = TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass,

                                                *MF);



    if (LaneVGPR == AMDGPU::NoRegister)

      // We have no VGPRs left for spilling SGPRs.

llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp

+6 −3
Original line number Diff line number Diff line
@@ -957,10 +957,13 @@ unsigned SIRegisterInfo::getPreloadedValue(const MachineFunction &MF, 
/// \brief Returns a register that is not used at any point in the function.

///        If all registers are used, then this function will return

//         AMDGPU::NoRegister.

unsigned SIRegisterInfo::findUnusedRegister(const MachineRegisterInfo &MRI,

                                           const TargetRegisterClass *RC) const {

unsigned

SIRegisterInfo::findUnusedRegister(const MachineRegisterInfo &MRI,

                                   const TargetRegisterClass *RC,

                                   const MachineFunction &MF) const {



  for (unsigned Reg : *RC)

    if (!MRI.isPhysRegUsed(Reg))

    if (MRI.isAllocatable(Reg) && !MRI.isPhysRegUsed(Reg))

      return Reg;

  return AMDGPU::NoRegister;

}

llvm/lib/Target/AMDGPU/SIRegisterInfo.h

+2 −1
Original line number Diff line number Diff line
@@ -185,7 +185,8 @@ public: 
  unsigned getNumSGPRsAllowed(const SISubtarget &ST, unsigned WaveCount) const;



  unsigned findUnusedRegister(const MachineRegisterInfo &MRI,

                              const TargetRegisterClass *RC) const;

                              const TargetRegisterClass *RC,

                              const MachineFunction &MF) const;



  unsigned getSGPR32PressureSet() const { return SGPR32SetID; };

  unsigned getVGPR32PressureSet() const { return VGPR32SetID; };