Commit b4a0766c authored by Matt Arsenault's avatar Matt Arsenault Committed by Matt Arsenault
Browse files

AMDGPU/GlobalISel: Select llvm.amdgcn.buffer.atomic.cmpswap

parent 9109cccb

llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

+4 −1
Original line number Diff line number Diff line
@@ -2698,6 +2698,9 @@ static unsigned getBufferAtomicPseudo(Intrinsic::ID IntrID) { 
  case Intrinsic::amdgcn_raw_buffer_atomic_dec:

  case Intrinsic::amdgcn_struct_buffer_atomic_dec:

    return AMDGPU::G_AMDGPU_BUFFER_ATOMIC_DEC;

  case Intrinsic::amdgcn_raw_buffer_atomic_cmpswap:

  case Intrinsic::amdgcn_struct_buffer_atomic_cmpswap:

    return AMDGPU::G_AMDGPU_BUFFER_ATOMIC_CMPSWAP;

  default:

    llvm_unreachable("unhandled atomic opcode");

  }
@@ -2729,7 +2732,7 @@ bool AMDGPULegalizerInfo::legalizeBufferAtomic(MachineInstr &MI, 
  const bool HasVIndex = MI.getNumOperands() == NumVIndexOps;

  Register VIndex;

  if (HasVIndex) {

    VIndex = MI.getOperand(4).getReg();

    VIndex = MI.getOperand(4 + OpOffset).getReg();

    ++OpOffset;

  }

llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

+26 −0
Original line number Diff line number Diff line
@@ -3159,6 +3159,32 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { 
    // initialized.

    break;

  }

  case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_CMPSWAP: {

    // vdata_out

    OpdsMapping[0] = getVGPROpMapping(MI.getOperand(0).getReg(), MRI, *TRI);



    // vdata_in

    OpdsMapping[1] = getVGPROpMapping(MI.getOperand(1).getReg(), MRI, *TRI);



    // cmp

    OpdsMapping[2] = getVGPROpMapping(MI.getOperand(2).getReg(), MRI, *TRI);



    // rsrc

    OpdsMapping[3] = getSGPROpMapping(MI.getOperand(3).getReg(), MRI, *TRI);



    // vindex

    OpdsMapping[4] = getVGPROpMapping(MI.getOperand(4).getReg(), MRI, *TRI);



    // voffset

    OpdsMapping[5] = getVGPROpMapping(MI.getOperand(5).getReg(), MRI, *TRI);



    // soffset

    OpdsMapping[6] = getSGPROpMapping(MI.getOperand(6).getReg(), MRI, *TRI);



    // Any remaining operands are immediates and were correctly null

    // initialized.

    break;

  }

  case AMDGPU::G_INTRINSIC: {

    switch (MI.getIntrinsicID()) {

    default:

llvm/lib/Target/AMDGPU/BUFInstructions.td

+12 −13
Original line number Diff line number Diff line
@@ -1443,14 +1443,13 @@ defm : BufferAtomicPatterns_NO_RTN<SIbuffer_atomic_pk_fadd, v2f16, "BUFFER_ATOMI 


def : GCNPat<

  (SIbuffer_atomic_cmpswap

      i32:$data, i32:$cmp, v4i32:$rsrc, 0,

      0, i32:$soffset, timm:$offset,

      timm:$cachepolicy, 0),

      i32:$data, i32:$cmp, v4i32:$rsrc, 0, 0, i32:$soffset,

      timm:$offset, timm:$cachepolicy, 0),

  (EXTRACT_SUBREG

    (BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN

      (REG_SEQUENCE VReg_64, $data, sub0, $cmp, sub1),

      $rsrc, $soffset, (as_i16imm $offset), (extract_slc $cachepolicy)),

    sub0)

      (REG_SEQUENCE VReg_64, VGPR_32:$data, sub0, VGPR_32:$cmp, sub1),

        SReg_128:$rsrc, SCSrc_b32:$soffset, (as_i16timm $offset),

        (extract_slc $cachepolicy)), sub0)

>;



def : GCNPat<
@@ -1460,8 +1459,8 @@ def : GCNPat< 
      timm:$cachepolicy, timm),

  (EXTRACT_SUBREG

    (BUFFER_ATOMIC_CMPSWAP_IDXEN_RTN

      (REG_SEQUENCE VReg_64, $data, sub0, $cmp, sub1),

      $vindex, $rsrc, $soffset, (as_i16imm $offset), (extract_slc $cachepolicy)),

      (REG_SEQUENCE VReg_64, VGPR_32:$data, sub0, VGPR_32:$cmp, sub1),

      VGPR_32:$vindex, SReg_128:$rsrc, SCSrc_b32:$soffset, (as_i16timm $offset), (extract_slc $cachepolicy)),

    sub0)

>;
@@ -1472,8 +1471,8 @@ def : GCNPat< 
      timm:$cachepolicy, 0),

  (EXTRACT_SUBREG

    (BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN

      (REG_SEQUENCE VReg_64, $data, sub0, $cmp, sub1),

      $voffset, $rsrc, $soffset, (as_i16imm $offset), (extract_slc $cachepolicy)),

      (REG_SEQUENCE VReg_64, VGPR_32:$data, sub0, VGPR_32:$cmp, sub1),

      VGPR_32:$voffset, SReg_128:$rsrc, SCSrc_b32:$soffset, (as_i16timm $offset), (extract_slc $cachepolicy)),

    sub0)

>;
@@ -1484,9 +1483,9 @@ def : GCNPat< 
      timm:$cachepolicy, timm),

  (EXTRACT_SUBREG

    (BUFFER_ATOMIC_CMPSWAP_BOTHEN_RTN

      (REG_SEQUENCE VReg_64, $data, sub0, $cmp, sub1),

      (REG_SEQUENCE VReg_64, $vindex, sub0, $voffset, sub1),

      $rsrc, $soffset, (as_i16imm $offset), (extract_slc $cachepolicy)),

      (REG_SEQUENCE VReg_64, VGPR_32:$data, sub0, VGPR_32:$cmp, sub1),

      (REG_SEQUENCE VReg_64, VGPR_32:$vindex, sub0, VGPR_32:$voffset, sub1),

      SReg_128:$rsrc, SCSrc_b32:$soffset, (as_i16timm $offset), (extract_slc $cachepolicy)),

    sub0)

>;

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.cmpswap.ll

0 → 100644
+195 −0
Original line number Diff line number Diff line 
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -verify-machineinstrs -o - %s | FileCheck %s



; Natural mapping

define amdgpu_ps float @raw_buffer_atomic_cmpswap_i32__vgpr_val__vgpr_cmp__sgpr_rsrc__vgpr_voffset__sgpr_soffset(i32 %val, i32 %cmp, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_atomic_cmpswap_i32__vgpr_val__vgpr_cmp__sgpr_rsrc__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1

  ; CHECK:   [[BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN:%[0-9]+]]:vreg_64 = BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom "TargetCustom7", align 1, addrspace 4)

  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN]].sub0

  ; CHECK:   $vgpr0 = COPY [[COPY8]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %ret = call i32 @llvm.amdgcn.raw.buffer.atomic.cmpswap.i32(i32 %val, i32 %cmp, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)

  %cast = bitcast i32 %ret to float

  ret float %cast

}



; Natural mapping

define amdgpu_ps void @raw_buffer_atomic_cmpswap_i32_noret__vgpr_val__vgpr_cmp__sgpr_rsrc__vgpr_voffset__sgpr_soffset(i32 %val, i32 %cmp, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_atomic_cmpswap_i32_noret__vgpr_val__vgpr_cmp__sgpr_rsrc__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1

  ; CHECK:   [[BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN:%[0-9]+]]:vreg_64 = BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom "TargetCustom7", align 1, addrspace 4)

  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN]].sub0

  ; CHECK:   S_ENDPGM 0

  %ret = call i32 @llvm.amdgcn.raw.buffer.atomic.cmpswap.i32(i32 %val, i32 %cmp, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)

  ret void

}



; All operands need regbank legalization

define amdgpu_ps float @raw_buffer_atomic_cmpswap_i32__sgpr_val__sgpr_cmp__vgpr_rsrc__sgpr_voffset__vgpr_soffset(i32 inreg %val, i32 inreg %cmp, <4 x i32> %rsrc, i32 inreg %voffset, i32 %soffset) {

  ; CHECK-LABEL: name: raw_buffer_atomic_cmpswap_i32__sgpr_val__sgpr_cmp__vgpr_rsrc__sgpr_voffset__vgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   successors: %bb.2(0x80000000)

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3

  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY]]

  ; CHECK:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY1]]

  ; CHECK:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]

  ; CHECK:   [[COPY11:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; CHECK:   [[COPY12:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; CHECK: bb.2:

  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

  ; CHECK:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]].sub0, implicit $exec

  ; CHECK:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]].sub1, implicit $exec

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1

  ; CHECK:   [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE1]], [[COPY11]], implicit $exec

  ; CHECK:   [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY12]].sub0, implicit $exec

  ; CHECK:   [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY12]].sub1, implicit $exec

  ; CHECK:   [[REG_SEQUENCE2:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_2]], %subreg.sub0, [[V_READFIRSTLANE_B32_3]], %subreg.sub1

  ; CHECK:   [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE2]], [[COPY12]], implicit $exec

  ; CHECK:   [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_1]], [[V_CMP_EQ_U64_e64_]], implicit-def $scc

  ; CHECK:   [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3

  ; CHECK:   [[V_READFIRSTLANE_B32_4:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]], implicit $exec

  ; CHECK:   [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[V_READFIRSTLANE_B32_4]], [[COPY7]], implicit $exec

  ; CHECK:   [[S_AND_B64_1:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U32_e64_]], [[S_AND_B64_]], implicit-def $scc

  ; CHECK:   [[REG_SEQUENCE4:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY8]], %subreg.sub0, [[COPY9]], %subreg.sub1

  ; CHECK:   [[BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN:%[0-9]+]]:vreg_64 = BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN [[REG_SEQUENCE4]], [[COPY10]], [[REG_SEQUENCE3]], [[V_READFIRSTLANE_B32_4]], 0, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom "TargetCustom7", align 1, addrspace 4)

  ; CHECK:   [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN]].sub0

  ; CHECK:   [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_1]], implicit-def $exec, implicit-def $scc, implicit $exec

  ; CHECK:   $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc

  ; CHECK:   S_CBRANCH_EXECNZ %bb.2, implicit $exec

  ; CHECK: bb.3:

  ; CHECK:   successors: %bb.4(0x80000000)

  ; CHECK:   $exec = S_MOV_B64_term [[S_MOV_B64_term]]

  ; CHECK: bb.4:

  ; CHECK:   $vgpr0 = COPY [[COPY13]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %ret = call i32 @llvm.amdgcn.raw.buffer.atomic.cmpswap.i32(i32 %val, i32 %cmp, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)

  %cast = bitcast i32 %ret to float

  ret float %cast

}



; All operands need regbank legalization

define amdgpu_ps void @raw_buffer_atomic_cmpswap_i32_noret__sgpr_val__sgpr_cmp__vgpr_rsrc__sgpr_voffset__vgpr_soffset(i32 inreg %val, i32 inreg %cmp, <4 x i32> %rsrc, i32 inreg %voffset, i32 %soffset) {

  ; CHECK-LABEL: name: raw_buffer_atomic_cmpswap_i32_noret__sgpr_val__sgpr_cmp__vgpr_rsrc__sgpr_voffset__vgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   successors: %bb.2(0x80000000)

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4

  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr3

  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr4

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3

  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY]]

  ; CHECK:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY1]]

  ; CHECK:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]

  ; CHECK:   [[COPY11:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1

  ; CHECK:   [[COPY12:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3

  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec

  ; CHECK: bb.2:

  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)

  ; CHECK:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]].sub0, implicit $exec

  ; CHECK:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]].sub1, implicit $exec

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1

  ; CHECK:   [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE1]], [[COPY11]], implicit $exec

  ; CHECK:   [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY12]].sub0, implicit $exec

  ; CHECK:   [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY12]].sub1, implicit $exec

  ; CHECK:   [[REG_SEQUENCE2:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_2]], %subreg.sub0, [[V_READFIRSTLANE_B32_3]], %subreg.sub1

  ; CHECK:   [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE2]], [[COPY12]], implicit $exec

  ; CHECK:   [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_1]], [[V_CMP_EQ_U64_e64_]], implicit-def $scc

  ; CHECK:   [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3

  ; CHECK:   [[V_READFIRSTLANE_B32_4:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]], implicit $exec

  ; CHECK:   [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[V_READFIRSTLANE_B32_4]], [[COPY7]], implicit $exec

  ; CHECK:   [[S_AND_B64_1:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U32_e64_]], [[S_AND_B64_]], implicit-def $scc

  ; CHECK:   [[REG_SEQUENCE4:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY8]], %subreg.sub0, [[COPY9]], %subreg.sub1

  ; CHECK:   [[BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN:%[0-9]+]]:vreg_64 = BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN [[REG_SEQUENCE4]], [[COPY10]], [[REG_SEQUENCE3]], [[V_READFIRSTLANE_B32_4]], 0, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom "TargetCustom7", align 1, addrspace 4)

  ; CHECK:   [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN]].sub0

  ; CHECK:   [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_1]], implicit-def $exec, implicit-def $scc, implicit $exec

  ; CHECK:   $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc

  ; CHECK:   S_CBRANCH_EXECNZ %bb.2, implicit $exec

  ; CHECK: bb.3:

  ; CHECK:   successors: %bb.4(0x80000000)

  ; CHECK:   $exec = S_MOV_B64_term [[S_MOV_B64_term]]

  ; CHECK: bb.4:

  ; CHECK:   S_ENDPGM 0

  %ret = call i32 @llvm.amdgcn.raw.buffer.atomic.cmpswap.i32(i32 %val, i32 %cmp, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)

  ret void

}



define amdgpu_ps float @raw_buffer_atomic_cmpswap_i32__vgpr_val__vgpr_cmp__sgpr_rsrc__vgpr_voffset__sgpr_soffset__voffset_add4095(i32 %val, i32 %cmp, <4 x i32> inreg %rsrc, i32 %voffset.base, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_atomic_cmpswap_i32__vgpr_val__vgpr_cmp__sgpr_rsrc__vgpr_voffset__sgpr_soffset__voffset_add4095

  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2

  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3

  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4

  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5

  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2

  ; CHECK:   [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6

  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3

  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1

  ; CHECK:   [[BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN:%[0-9]+]]:vreg_64 = BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 4095, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom "TargetCustom7" + 4095, align 1, addrspace 4)

  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN]].sub0

  ; CHECK:   $vgpr0 = COPY [[COPY8]]

  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0

  %voffset = add i32 %voffset.base, 4095

  %ret = call i32 @llvm.amdgcn.raw.buffer.atomic.cmpswap.i32(i32 %val, i32 %cmp, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)

  %cast = bitcast i32 %ret to float

  ret float %cast

}





; FIXME: 64-bit not handled

; ; Natural mapping

; define amdgpu_ps <2 x float> @raw_buffer_atomic_cmpswap_i64__vgpr_val__vgpr_cmp__sgpr_rsrc__vgpr_voffset__sgpr_soffset(i64 %val, i64 %cmp, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {

;   %ret = call i64 @llvm.amdgcn.raw.buffer.atomic.cmpswap.i64(i64 %val, i64 %cmp, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)

;   %cast = bitcast i64 %ret to <2 x float>

;   ret <2 x float> %cast

; }



; define amdgpu_ps void @raw_buffer_atomic_cmpswap_i64_noret__vgpr_val__vgpr_cmp__sgpr_rsrc__vgpr_voffset__sgpr_soffset(i64 %val, i64 %cmp, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {

;   %ret = call i64 @llvm.amdgcn.raw.buffer.atomic.cmpswap.i64(i64 %val, i64 %cmp, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)

;   ret void

; }



declare i32 @llvm.amdgcn.raw.buffer.atomic.cmpswap.i32(i32, i32, <4 x i32>, i32, i32, i32 immarg) #0

declare i64 @llvm.amdgcn.raw.buffer.atomic.cmpswap.i64(i64, i64, <4 x i32>, i32, i32, i32 immarg) #0



attributes #0 = { nounwind }

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.cmpswap.ll

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