This reverts a long string of commits to the Hexagon backend. These

#include "llvm/CodeGen/MachineBasicBlock.h"

#include "llvm/ADT/DenseMap.h"

#include <map>

namespace llvm {

class MachineLoopInfo;

class MachineDominatorTree;

class InstrItineraryData;

class DefaultVLIWScheduler;

class ScheduleDAGInstrs;

class SUnit;

class DFAPacketizer {

  // reserveResources - Reserve the resources occupied by a machine

  // instruction and change the current state to reflect that change.

  void reserveResources(llvm::MachineInstr *MI);

  const InstrItineraryData *getInstrItins() const { return InstrItins; }

};

// VLIWPacketizerList - Implements a simple VLIW packetizer using DFA. The

// and machine resource is marked as taken. If any dependency is found, a target

// API call is made to prune the dependence.

class VLIWPacketizerList {

protected:

  const TargetMachine &TM;

  const MachineFunction &MF;

  const TargetInstrInfo *TII;

  // The VLIW Scheduler.

  DefaultVLIWScheduler *VLIWScheduler;

  // Encapsulate data types not exposed to the target interface.

  ScheduleDAGInstrs *SchedulerImpl;

protected:

  // Vector of instructions assigned to the current packet.

  std::vector<MachineInstr*> CurrentPacketMIs;

  // DFA resource tracker.

  DFAPacketizer *ResourceTracker;

  // Generate MI -> SU map.

  std::map<MachineInstr*, SUnit*> MIToSUnit;

  // Scheduling units.

  std::vector<SUnit> SUnits;

public:

  VLIWPacketizerList(

  DFAPacketizer *getResourceTracker() {return ResourceTracker;}

  // addToPacket - Add MI to the current packet.

  virtual MachineBasicBlock::iterator addToPacket(MachineInstr *MI) {

    MachineBasicBlock::iterator MII = MI;

    CurrentPacketMIs.push_back(MI);

    ResourceTracker->reserveResources(MI);

    return MII;

  }

  void addToPacket(MachineInstr *MI);

  // endPacket - End the current packet.

  void endPacket(MachineBasicBlock *MBB, MachineInstr *MI);

  // initPacketizerState - perform initialization before packetizing

  // an instruction. This function is supposed to be overrided by

  // the target dependent packetizer.

  virtual void initPacketizerState(void) { return; }

  void endPacket(MachineBasicBlock *MBB, MachineInstr *I);

  // ignorePseudoInstruction - Ignore bundling of pseudo instructions.

  virtual bool ignorePseudoInstruction(MachineInstr *I,

                                       MachineBasicBlock *MBB) {

    return false;

  }

  bool ignorePseudoInstruction(MachineInstr *I, MachineBasicBlock *MBB);

  // isSoloInstruction - return true if instruction MI can not be packetized

  // with any other instruction, which means that MI itself is a packet.

  virtual bool isSoloInstruction(MachineInstr *MI) {

    return true;

  }

  // isSoloInstruction - return true if instruction I must end previous

  // packet.

  bool isSoloInstruction(MachineInstr *I);

  // isLegalToPacketizeTogether - Is it legal to packetize SUI and SUJ

  // together.

  virtual bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) {

    return false;

  }

};

}

//

//===----------------------------------------------------------------------===//

#include "llvm/CodeGen/ScheduleDAGInstrs.h"

#include "llvm/CodeGen/DFAPacketizer.h"

#include "llvm/CodeGen/MachineInstr.h"

#include "llvm/CodeGen/MachineInstrBundle.h"

#include "llvm/CodeGen/ScheduleDAGInstrs.h"

#include "llvm/Target/TargetInstrInfo.h"

#include "llvm/MC/MCInstrItineraries.h"

using namespace llvm;

  reserveResources(&MID);

}

namespace llvm {

namespace {

// DefaultVLIWScheduler - This class extends ScheduleDAGInstrs and overrides

// Schedule method to build the dependence graph.

class DefaultVLIWScheduler : public ScheduleDAGInstrs {

  // Schedule - Actual scheduling work.

  void schedule();

};

}

} // end anonymous namespace

DefaultVLIWScheduler::DefaultVLIWScheduler(

  MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT,

  bool IsPostRA) : TM(MF.getTarget()), MF(MF)  {

  TII = TM.getInstrInfo();

  ResourceTracker = TII->CreateTargetScheduleState(&TM, 0);

  VLIWScheduler = new DefaultVLIWScheduler(MF, MLI, MDT, IsPostRA);

  SchedulerImpl = new DefaultVLIWScheduler(MF, MLI, MDT, IsPostRA);

}

// VLIWPacketizerList Dtor

VLIWPacketizerList::~VLIWPacketizerList() {

  if (VLIWScheduler)

    delete VLIWScheduler;

  if (ResourceTracker)

  delete SchedulerImpl;

  delete ResourceTracker;

}

// ignorePseudoInstruction - ignore pseudo instructions.

bool VLIWPacketizerList::ignorePseudoInstruction(MachineInstr *MI,

                                                 MachineBasicBlock *MBB) {

  if (MI->isDebugValue())

    return true;

  if (TII->isSchedulingBoundary(MI, MBB, MF))

    return true;

  return false;

}

// isSoloInstruction - return true if instruction I must end previous

// packet.

bool VLIWPacketizerList::isSoloInstruction(MachineInstr *I) {

  if (I->isInlineAsm())

    return true;

  return false;

}

// addToPacket - Add I to the current packet and reserve resource.

void VLIWPacketizerList::addToPacket(MachineInstr *MI) {

  CurrentPacketMIs.push_back(MI);

  ResourceTracker->reserveResources(MI);

}

// endPacket - End the current packet, bundle packet instructions and reset

// DFA state.

void VLIWPacketizerList::endPacket(MachineBasicBlock *MBB,

                                         MachineInstr *MI) {

                                         MachineInstr *I) {

  if (CurrentPacketMIs.size() > 1) {

    MachineInstr *MIFirst = CurrentPacketMIs.front();

    finalizeBundle(*MBB, MIFirst, MI);

    finalizeBundle(*MBB, MIFirst, I);

  }

  CurrentPacketMIs.clear();

  ResourceTracker->clearResources();

void VLIWPacketizerList::PacketizeMIs(MachineBasicBlock *MBB,

                                      MachineBasicBlock::iterator BeginItr,

                                      MachineBasicBlock::iterator EndItr) {

  assert(VLIWScheduler && "VLIW Scheduler is not initialized!");

  VLIWScheduler->enterRegion(MBB, BeginItr, EndItr, MBB->size());

  VLIWScheduler->schedule();

  VLIWScheduler->exitRegion();

  assert(MBB->end() == EndItr && "Bad EndIndex");

  // Generate MI -> SU map.

  //std::map <MachineInstr*, SUnit*> MIToSUnit;

  MIToSUnit.clear();

  for (unsigned i = 0, e = VLIWScheduler->SUnits.size(); i != e; ++i) {

    SUnit *SU = &VLIWScheduler->SUnits[i];

    MIToSUnit[SU->getInstr()] = SU;

  }

  SchedulerImpl->enterRegion(MBB, BeginItr, EndItr, MBB->size());

  // Build the DAG without reordering instructions.

  SchedulerImpl->schedule();

  // Remember scheduling units.

  SUnits = SchedulerImpl->SUnits;

  // The main packetizer loop.

  for (; BeginItr != EndItr; ++BeginItr) {

    MachineInstr *MI = BeginItr;

    this->initPacketizerState();

    // Ignore pseudo instructions.

    if (ignorePseudoInstruction(MI, MBB))

      continue;

    // End the current packet if needed.

    if (this->isSoloInstruction(MI)) {

    if (isSoloInstruction(MI)) {

      endPacket(MBB, MI);

      continue;

    }

    // Ignore pseudo instructions.

    if (this->ignorePseudoInstruction(MI, MBB))

      continue;

    SUnit *SUI = MIToSUnit[MI];

    SUnit *SUI = SchedulerImpl->getSUnit(MI);

    assert(SUI && "Missing SUnit Info!");

    // Ask DFA if machine resource is available for MI.

      for (std::vector<MachineInstr*>::iterator VI = CurrentPacketMIs.begin(),

           VE = CurrentPacketMIs.end(); VI != VE; ++VI) {

        MachineInstr *MJ = *VI;

        SUnit *SUJ = MIToSUnit[MJ];

        SUnit *SUJ = SchedulerImpl->getSUnit(MJ);

        assert(SUJ && "Missing SUnit Info!");

        // Is it legal to packetize SUI and SUJ together.

        if (!this->isLegalToPacketizeTogether(SUI, SUJ)) {

        if (!isLegalToPacketizeTogether(SUI, SUJ)) {

          // Allow packetization if dependency can be pruned.

          if (!this->isLegalToPruneDependencies(SUI, SUJ)) {

          if (!isLegalToPruneDependencies(SUI, SUJ)) {

            // End the packet if dependency cannot be pruned.

            endPacket(MBB, MI);

            break;

    }

    // Add MI to the current packet.

    BeginItr = this->addToPacket(MI);

    addToPacket(MI);

  } // For all instructions in BB.

  // End any packet left behind.

  endPacket(MBB, EndItr);

  SchedulerImpl->exitRegion();

}

add_llvm_target(HexagonCodeGen

  HexagonAsmPrinter.cpp

  HexagonCFGOptimizer.cpp

  HexagonCallingConvLower.cpp

  HexagonCFGOptimizer.cpp

  HexagonExpandPredSpillCode.cpp

  HexagonFrameLowering.cpp

  HexagonHardwareLoops.cpp

  HexagonMCInstLower.cpp

  HexagonInstrInfo.cpp

  HexagonISelDAGToDAG.cpp

  HexagonISelLowering.cpp

  HexagonInstrInfo.cpp

  HexagonMCInstLower.cpp

  HexagonPeephole.cpp

  HexagonRegisterInfo.cpp

  HexagonRemoveSZExtArgs.cpp

  HexagonSubtarget.cpp

  HexagonTargetMachine.cpp

  HexagonTargetObjectFile.cpp

  HexagonVLIWPacketizer.cpp

  HexagonNewValueJump.cpp

  HexagonCopyToCombine.cpp

)

add_subdirectory(TargetInfo)

  FunctionPass *createHexagonHardwareLoops();

  FunctionPass *createHexagonPeephole();

  FunctionPass *createHexagonFixupHwLoops();

  FunctionPass *createHexagonNewValueJump();

  FunctionPass *createHexagonCopyToCombine();

  FunctionPass *createHexagonPacketizer();

/* TODO: object output.

  MCCodeEmitter *createHexagonMCCodeEmitter(const Target &,