Commit b3369522 authored by Bill Schmidt's avatar Bill Schmidt
Browse files

Merging r214716: 

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r214716 | uweigand | 2014-08-04 08:27:12 -0500 (Mon, 04 Aug 2014) | 9 lines

[PowerPC] MULHU/MULHS are not legal for vector types

I ran into some test failures where common code changed vector division
by constant into a multiply-high operation (MULHU).  But these are not
implemented by the back-end, so we failed to recognize the insn.

Fixed by marking MULHU/MULHS as Expand for vector types.


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llvm-svn: 214818
parent 444a522e

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

+2 −0
Original line number Diff line number Diff line
@@ -453,6 +453,8 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM) 
      setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);

      setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);

      setOperationAction(ISD::BUILD_VECTOR, VT, Expand);

      setOperationAction(ISD::MULHU, VT, Expand);

      setOperationAction(ISD::MULHS, VT, Expand);

      setOperationAction(ISD::UMUL_LOHI, VT, Expand);

      setOperationAction(ISD::SMUL_LOHI, VT, Expand);

      setOperationAction(ISD::UDIVREM, VT, Expand);

llvm/test/CodeGen/PowerPC/vec_urem_const.ll

0 → 100644
+10 −0
Original line number Diff line number Diff line 
; RUN: llc -mcpu=pwr6 -mattr=+altivec < %s



; Common code used to replace the urem by a mulhu, and compilation would

; then crash since mulhu isn't supported on vector types.



define <4 x i32> @test(<4 x i32> %x) {

entry:

  %0 = urem <4 x i32> %x, <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>

  ret <4 x i32> %0

}