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Commit b1aba037 authored Dec 08, 2019 by David Green

[ARM] Enable MVE masked loads and stores

With the extra optimisations we have done, these should now be fine to
enable by default. Which is what this patch does.

Differential Revision: https://reviews.llvm.org/D70968

parent 966fac19

llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp

+1 −1

Original line number	Diff line number	Diff line
		@@ -37,7 +37,7 @@ using namespace llvm;
		#define DEBUG_TYPE "armtti"

		static cl::opt<bool> EnableMaskedLoadStores(
		"enable-arm-maskedldst", cl::Hidden, cl::init(false),
		"enable-arm-maskedldst", cl::Hidden, cl::init(true),
		cl::desc("Enable the generation of masked loads and stores"));

		static cl::opt<bool> DisableLowOverheadLoops(

llvm/test/CodeGen/Thumb2/LowOverheadLoops/cond-vector-reduce-mve-codegen.ll

+1 −1

Original line number	Diff line number	Diff line
		; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -enable-arm-maskedldst=true -disable-mve-tail-predication=false --verify-machineinstrs %s -o - \| FileCheck %s
		; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -disable-mve-tail-predication=false --verify-machineinstrs %s -o - \| FileCheck %s

		; CHECK-LABEL: vpsel_mul_reduce_add
		; CHECK: dls lr, lr

llvm/test/CodeGen/Thumb2/LowOverheadLoops/fast-fp-loops.ll

+1 −1

Original line number	Diff line number	Diff line
		; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
		; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp,+fp-armv8d16sp,+fp16,+fpregs,+fullfp16 -enable-arm-maskedldst=true -disable-mve-tail-predication=false %s -o - \| FileCheck %s
		; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp,+fp-armv8d16sp,+fp16,+fpregs,+fullfp16 -disable-mve-tail-predication=false %s -o - \| FileCheck %s

		define arm_aapcs_vfpcc void @fast_float_mul(float* nocapture %a, float* nocapture readonly %b, float* nocapture readonly %c, i32 %N) {
		; CHECK-LABEL: fast_float_mul:

llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-tail-data-types.ll

+1 −1

Original line number	Diff line number	Diff line
		; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
		; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -disable-mve-tail-predication=false -enable-arm-maskedldst=true %s -o - \| FileCheck %s
		; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -disable-mve-tail-predication=false %s -o - \| FileCheck %s

		define arm_aapcs_vfpcc i32 @test_acc_scalar_char(i8 zeroext %a, i8* nocapture readonly %b, i32 %N) {
		; CHECK-LABEL: test_acc_scalar_char:

llvm/test/CodeGen/Thumb2/LowOverheadLoops/vector-arith-codegen.ll

+1 −1

Original line number	Diff line number	Diff line
		; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
		; RUN: llc -mtriple=armv8.1m.main -mattr=+mve -enable-arm-maskedldst=true -disable-mve-tail-predication=false --verify-machineinstrs %s -o - \| FileCheck %s
		; RUN: llc -mtriple=armv8.1m.main -mattr=+mve -disable-mve-tail-predication=false --verify-machineinstrs %s -o - \| FileCheck %s

		define dso_local i32 @mul_reduce_add(i32* noalias nocapture readonly %a, i32* noalias nocapture readonly %b, i32 %N) {
		; CHECK-LABEL: mul_reduce_add: