Commit b0465c9c authored by Hans Wennborg's avatar Hans Wennborg
Browse files

Merging r295990: 

------------------------------------------------------------------------
r295990 | jvesely | 2017-02-23 08:12:21 -0800 (Thu, 23 Feb 2017) | 5 lines

AMDGPU/SI: Fix trunc i16 pattern

Hit on ASICs that support 16bit instructions.

Differential Revision: https://reviews.llvm.org/D30281
------------------------------------------------------------------------

llvm-svn: 296158
parent 1f7b90c8

llvm/lib/Target/AMDGPU/SIInstructions.td

+5 −0
Original line number Diff line number Diff line
@@ -996,6 +996,11 @@ def : Pat < 
  (V_CMP_EQ_U32_e64 (S_AND_B32 (i32 1), $a), (i32 1))

>;



def : Pat <

  (i1 (trunc i16:$a)),

  (V_CMP_EQ_U32_e64 (S_AND_B32 (i32 1), $a), (i32 1))

>;



def : Pat <

  (i1 (trunc i64:$a)),

  (V_CMP_EQ_U32_e64 (S_AND_B32 (i32 1),

llvm/lib/Target/AMDGPU/VOP1Instructions.td

+0 −6
Original line number Diff line number Diff line
@@ -607,12 +607,6 @@ def : Pat< 
  (COPY $src)

>;



def : Pat<

  (i1 (trunc i16:$src)),

  (COPY $src)

>;





def : Pat <

  (i16 (trunc i64:$src)),

  (EXTRACT_SUBREG $src, sub0)

llvm/test/CodeGen/AMDGPU/trunc.ll

+60 −31
Original line number Diff line number Diff line 
; RUN: llc -march=amdgcn -verify-machineinstrs< %s | FileCheck -check-prefix=SI %s

; RUN: llc -march=amdgcn -verify-machineinstrs< %s | FileCheck -check-prefix=GCN -check-prefix=SI %s

; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs< %s | FileCheck -check-prefix=GCN -check-prefix=VI  %s

; RUN: llc -march=r600 -mcpu=cypress < %s | FileCheck -check-prefix=EG %s



declare i32 @llvm.r600.read.tidig.x() nounwind readnone



define void @trunc_i64_to_i32_store(i32 addrspace(1)* %out, i64 %in) {

; SI-LABEL: {{^}}trunc_i64_to_i32_store:

; SI: s_load_dword [[SLOAD:s[0-9]+]], s[0:1], 0xb

; SI: v_mov_b32_e32 [[VLOAD:v[0-9]+]], [[SLOAD]]

; GCN-LABEL: {{^}}trunc_i64_to_i32_store:

; GCN: s_load_dword [[SLOAD:s[0-9]+]], s[0:1],

; GCN: v_mov_b32_e32 [[VLOAD:v[0-9]+]], [[SLOAD]]

; SI: buffer_store_dword [[VLOAD]]

; VI: flat_store_dword v[{{[0-9:]+}}], [[VLOAD]]



; EG-LABEL: {{^}}trunc_i64_to_i32_store:

; EG: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
@@ -18,12 +20,14 @@ define void @trunc_i64_to_i32_store(i32 addrspace(1)* %out, i64 %in) { 
  ret void

}



; SI-LABEL: {{^}}trunc_load_shl_i64:

; SI-DAG: s_load_dwordx2

; SI-DAG: s_load_dword [[SREG:s[0-9]+]],

; SI: s_lshl_b32 [[SHL:s[0-9]+]], [[SREG]], 2

; SI: v_mov_b32_e32 [[VSHL:v[0-9]+]], [[SHL]]

; SI: buffer_store_dword [[VSHL]],

; GCN-LABEL: {{^}}trunc_load_shl_i64:

; GCN-DAG: s_load_dwordx2

; GCN-DAG: s_load_dword [[SREG:s[0-9]+]],

; GCN: s_lshl_b32 [[SHL:s[0-9]+]], [[SREG]], 2

; GCN: v_mov_b32_e32 [[VSHL:v[0-9]+]], [[SHL]]

; SI: buffer_store_dword [[VSHL]]

; VI: flat_store_dword v[{{[0-9:]+}}], [[VSHL]]



define void @trunc_load_shl_i64(i32 addrspace(1)* %out, i64 %a) {

  %b = shl i64 %a, 2

  %result = trunc i64 %b to i32
@@ -31,15 +35,17 @@ define void @trunc_load_shl_i64(i32 addrspace(1)* %out, i64 %a) { 
  ret void

}



; SI-LABEL: {{^}}trunc_shl_i64:

; GCN-LABEL: {{^}}trunc_shl_i64:

; SI: s_load_dwordx2 s{{\[}}[[LO_SREG:[0-9]+]]:{{[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xd

; SI: s_lshl_b64 s{{\[}}[[LO_SHL:[0-9]+]]:{{[0-9]+\]}}, s{{\[}}[[LO_SREG]]:{{[0-9]+\]}}, 2

; SI: s_add_u32 s[[LO_SREG2:[0-9]+]], s[[LO_SHL]],

; SI: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], s[[LO_SREG2]]

; SI: s_addc_u32

; VI: s_load_dwordx2 s{{\[}}[[LO_SREG:[0-9]+]]:{{[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x34

; GCN: s_lshl_b64 s{{\[}}[[LO_SHL:[0-9]+]]:{{[0-9]+\]}}, s{{\[}}[[LO_SREG]]:{{[0-9]+\]}}, 2

; GCN: s_add_u32 s[[LO_SREG2:[0-9]+]], s[[LO_SHL]],

; GCN: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], s[[LO_SREG2]]

; GCN: s_addc_u32

; SI: buffer_store_dword v[[LO_VREG]],

; SI: v_mov_b32_e32

; SI: v_mov_b32_e32

; VI: flat_store_dword v[{{[0-9:]+}}], v[[LO_VREG]]

; GCN: v_mov_b32_e32

; GCN: v_mov_b32_e32

define void @trunc_shl_i64(i64 addrspace(1)* %out2, i32 addrspace(1)* %out, i64 %a) {

  %aa = add i64 %a, 234 ; Prevent shrinking store.

  %b = shl i64 %aa, 2
@@ -49,9 +55,9 @@ define void @trunc_shl_i64(i64 addrspace(1)* %out2, i32 addrspace(1)* %out, i64 
  ret void

}



; SI-LABEL: {{^}}trunc_i32_to_i1:

; SI: v_and_b32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}}

; SI: v_cmp_eq_u32

; GCN-LABEL: {{^}}trunc_i32_to_i1:

; GCN: v_and_b32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}}

; GCN: v_cmp_eq_u32

define void @trunc_i32_to_i1(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) {

  %a = load i32, i32 addrspace(1)* %ptr, align 4

  %trunc = trunc i32 %a to i1
@@ -60,9 +66,30 @@ define void @trunc_i32_to_i1(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) { 
  ret void

}



; SI-LABEL: {{^}}sgpr_trunc_i32_to_i1:

; SI: s_and_b32 s{{[0-9]+}}, 1, s{{[0-9]+}}

; SI: v_cmp_eq_u32

; GCN-LABEL: {{^}}trunc_i8_to_i1:

; GCN: v_and_b32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}}

; GCN: v_cmp_eq_u32

define void @trunc_i8_to_i1(i8 addrspace(1)* %out, i8 addrspace(1)* %ptr) {

  %a = load i8, i8 addrspace(1)* %ptr, align 4

  %trunc = trunc i8 %a to i1

  %result = select i1 %trunc, i8 1, i8 0

  store i8 %result, i8 addrspace(1)* %out, align 4

  ret void

}



; GCN-LABEL: {{^}}sgpr_trunc_i16_to_i1:

; GCN: s_and_b32 s{{[0-9]+}}, 1, s{{[0-9]+}}

; GCN: v_cmp_eq_u32

define void @sgpr_trunc_i16_to_i1(i16 addrspace(1)* %out, i16 %a) {

  %trunc = trunc i16 %a to i1

  %result = select i1 %trunc, i16 1, i16 0

  store i16 %result, i16 addrspace(1)* %out, align 4

  ret void

}



; GCN-LABEL: {{^}}sgpr_trunc_i32_to_i1:

; GCN: s_and_b32 s{{[0-9]+}}, 1, s{{[0-9]+}}

; GCN: v_cmp_eq_u32

define void @sgpr_trunc_i32_to_i1(i32 addrspace(1)* %out, i32 %a) {

  %trunc = trunc i32 %a to i1

  %result = select i1 %trunc, i32 1, i32 0
@@ -70,11 +97,12 @@ define void @sgpr_trunc_i32_to_i1(i32 addrspace(1)* %out, i32 %a) { 
  ret void

}



; SI-LABEL: {{^}}s_trunc_i64_to_i1:

; GCN-LABEL: {{^}}s_trunc_i64_to_i1:

; SI: s_load_dwordx2 s{{\[}}[[SLO:[0-9]+]]:{{[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0xb

; SI: s_and_b32 [[MASKED:s[0-9]+]], 1, s[[SLO]]

; SI: v_cmp_eq_u32_e64 s{{\[}}[[VLO:[0-9]+]]:[[VHI:[0-9]+]]], [[MASKED]], 1{{$}}

; SI: v_cndmask_b32_e64 {{v[0-9]+}}, -12, 63, s{{\[}}[[VLO]]:[[VHI]]]

; VI: s_load_dwordx2 s{{\[}}[[SLO:[0-9]+]]:{{[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0x2c

; GCN: s_and_b32 [[MASKED:s[0-9]+]], 1, s[[SLO]]

; GCN: v_cmp_eq_u32_e64 s{{\[}}[[VLO:[0-9]+]]:[[VHI:[0-9]+]]], [[MASKED]], 1{{$}}

; GCN: v_cndmask_b32_e64 {{v[0-9]+}}, -12, 63, s{{\[}}[[VLO]]:[[VHI]]]

define void @s_trunc_i64_to_i1(i32 addrspace(1)* %out, i64 %x) {

  %trunc = trunc i64 %x to i1

  %sel = select i1 %trunc, i32 63, i32 -12
@@ -82,11 +110,12 @@ define void @s_trunc_i64_to_i1(i32 addrspace(1)* %out, i64 %x) { 
  ret void

}



; SI-LABEL: {{^}}v_trunc_i64_to_i1:

; GCN-LABEL: {{^}}v_trunc_i64_to_i1:

; SI: buffer_load_dwordx2 v{{\[}}[[VLO:[0-9]+]]:{{[0-9]+\]}}

; SI: v_and_b32_e32 [[MASKED:v[0-9]+]], 1, v[[VLO]]

; SI: v_cmp_eq_u32_e32 vcc, 1, [[MASKED]]

; SI: v_cndmask_b32_e64 {{v[0-9]+}}, -12, 63, vcc

; VI: flat_load_dwordx2 v{{\[}}[[VLO:[0-9]+]]:{{[0-9]+\]}}

; GCN: v_and_b32_e32 [[MASKED:v[0-9]+]], 1, v[[VLO]]

; GCN: v_cmp_eq_u32_e32 vcc, 1, [[MASKED]]

; GCN: v_cndmask_b32_e64 {{v[0-9]+}}, -12, 63, vcc

define void @v_trunc_i64_to_i1(i32 addrspace(1)* %out, i64 addrspace(1)* %in) {

  %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone

  %gep = getelementptr i64, i64 addrspace(1)* %in, i32 %tid