Commit a67db836 authored by Luke Geeson's avatar Luke Geeson
Browse files

[AArch64] Make Read Write System Registers Read Only 

This patch makes the following System Registers Read Only:

 - CurrentEL
 - ICH_MISR_EL2
 - PMBIDR_EL1
 - PMSIDR_EL1

as found in:
https://developer.arm.com/docs/ddi0595/e/aarch64-system-registers

Relative line numbers were also added to the tests so we get more
informative error messages on failure.

Change-Id: I963b4f01ca5737b58f9e8e7abe9ca1d99e328758
parent fcea7fbd

llvm/lib/Target/AArch64/AArch64SystemOperands.td

+4 −4
Original line number Diff line number Diff line
@@ -844,7 +844,7 @@ def : RWSysReg<"SP_EL2", 0b11, 0b110, 0b0100, 0b0001, 0b000>; 
def : RWSysReg<"SPSel",              0b11, 0b000, 0b0100, 0b0010, 0b000>;

def : RWSysReg<"NZCV",               0b11, 0b011, 0b0100, 0b0010, 0b000>;

def : RWSysReg<"DAIF",               0b11, 0b011, 0b0100, 0b0010, 0b001>;

def : RWSysReg<"CurrentEL",          0b11, 0b000, 0b0100, 0b0010, 0b010>;

def : ROSysReg<"CurrentEL",          0b11, 0b000, 0b0100, 0b0010, 0b010>;

def : RWSysReg<"SPSR_irq",           0b11, 0b100, 0b0100, 0b0011, 0b000>;

def : RWSysReg<"SPSR_abt",           0b11, 0b100, 0b0100, 0b0011, 0b001>;

def : RWSysReg<"SPSR_und",           0b11, 0b100, 0b0100, 0b0011, 0b010>;
@@ -1184,7 +1184,7 @@ def : RWSysReg<"ICH_AP1R1_EL2", 0b11, 0b100, 0b1100, 0b1001, 0b001>; 
def : RWSysReg<"ICH_AP1R2_EL2",      0b11, 0b100, 0b1100, 0b1001, 0b010>;

def : RWSysReg<"ICH_AP1R3_EL2",      0b11, 0b100, 0b1100, 0b1001, 0b011>;

def : RWSysReg<"ICH_HCR_EL2",        0b11, 0b100, 0b1100, 0b1011, 0b000>;

def : RWSysReg<"ICH_MISR_EL2",       0b11, 0b100, 0b1100, 0b1011, 0b010>;

def : ROSysReg<"ICH_MISR_EL2",       0b11, 0b100, 0b1100, 0b1011, 0b010>;

def : RWSysReg<"ICH_VMCR_EL2",       0b11, 0b100, 0b1100, 0b1011, 0b111>;

def : RWSysReg<"ICH_LR0_EL2",        0b11, 0b100, 0b1100, 0b1100, 0b000>;

def : RWSysReg<"ICH_LR1_EL2",        0b11, 0b100, 0b1100, 0b1100, 0b001>;
@@ -1258,7 +1258,7 @@ let Requires = [{ {AArch64::FeatureSPE} }] in { 
def : RWSysReg<"PMBLIMITR_EL1", 0b11, 0b000, 0b1001, 0b1010, 0b000>;

def : RWSysReg<"PMBPTR_EL1",    0b11, 0b000, 0b1001, 0b1010, 0b001>;

def : RWSysReg<"PMBSR_EL1",     0b11, 0b000, 0b1001, 0b1010, 0b011>;

def : RWSysReg<"PMBIDR_EL1",    0b11, 0b000, 0b1001, 0b1010, 0b111>;

def : ROSysReg<"PMBIDR_EL1",    0b11, 0b000, 0b1001, 0b1010, 0b111>;

def : RWSysReg<"PMSCR_EL2",     0b11, 0b100, 0b1001, 0b1001, 0b000>;

def : RWSysReg<"PMSCR_EL12",    0b11, 0b101, 0b1001, 0b1001, 0b000>;

def : RWSysReg<"PMSCR_EL1",     0b11, 0b000, 0b1001, 0b1001, 0b000>;
@@ -1267,7 +1267,7 @@ def : RWSysReg<"PMSIRR_EL1", 0b11, 0b000, 0b1001, 0b1001, 0b011>; 
def : RWSysReg<"PMSFCR_EL1",    0b11, 0b000, 0b1001, 0b1001, 0b100>;

def : RWSysReg<"PMSEVFR_EL1",   0b11, 0b000, 0b1001, 0b1001, 0b101>;

def : RWSysReg<"PMSLATFR_EL1",  0b11, 0b000, 0b1001, 0b1001, 0b110>;

def : RWSysReg<"PMSIDR_EL1",    0b11, 0b000, 0b1001, 0b1001, 0b111>;

def : ROSysReg<"PMSIDR_EL1",    0b11, 0b000, 0b1001, 0b1001, 0b111>;

}



// v8.2a "RAS extension" registers

llvm/test/MC/AArch64/arm64-system-encoding.s

+4 −2
Original line number Diff line number Diff line
@@ -88,7 +88,6 @@ foo: 
  msr CPTR_EL2, x3

  msr CPTR_EL3, x3

  msr CSSELR_EL1, x3

  msr CURRENTEL, x3

  msr DACR32_EL2, x3

  msr ESR_EL1, x3

  msr ESR_EL2, x3
@@ -168,7 +167,6 @@ foo: 
; CHECK: msr CPTR_EL2, x3               ; encoding: [0x43,0x11,0x1c,0xd5]

; CHECK: msr CPTR_EL3, x3               ; encoding: [0x43,0x11,0x1e,0xd5]

; CHECK: msr CSSELR_EL1, x3             ; encoding: [0x03,0x00,0x1a,0xd5]

; CHECK: msr CurrentEL, x3              ; encoding: [0x43,0x42,0x18,0xd5]

; CHECK: msr DACR32_EL2, x3             ; encoding: [0x03,0x30,0x1c,0xd5]

; CHECK: msr ESR_EL1, x3                ; encoding: [0x03,0x52,0x18,0xd5]

; CHECK: msr ESR_EL2, x3                ; encoding: [0x03,0x52,0x1c,0xd5]
@@ -219,6 +217,10 @@ foo: 
; CHECK: msr  S0_0_C0_C0_0, x0          ; encoding: [0x00,0x00,0x00,0xd5]

; CHECK: msr  S1_2_C3_C4_5, x2          ; encoding: [0xa2,0x34,0x0a,0xd5]



// Readonly system registers: writing to them gives an error

  msr CURRENTEL, x3

; CHECK-ERRORS: :[[@LINE-1]]:7: error: expected writable system register or pstate



  mrs x3, ACTLR_EL1

  mrs x3, ACTLR_EL2

  mrs x3, ACTLR_EL3

llvm/test/MC/AArch64/armv8.2a-statistical-profiling.s

+19 −9
Original line number Diff line number Diff line 
// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+spe < %s | FileCheck %s

// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=neoverse-n1 < %s | FileCheck %s

// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding < %s 2>&1 | FileCheck --check-prefix=NO_SPE %s

// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+spe       < %s 2> %t | FileCheck %s

// RUN: FileCheck --check-prefix=ERROR %s < %t

// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=neoverse-n1 < %s 2> %t | FileCheck %s

// RUN: FileCheck --check-prefix=ERROR %s < %t

// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding                   < %s 2> %t | FileCheck --check-prefix=NO_SPE_OUT %s

// RUN: FileCheck --check-prefix=NO_SPE %s < %t



// NO_SPE_OUT-NOT: msr

// NO_SPE_OUT-NOT: mrs

// NO_SPE_OUT-NOT: psb



  psb csync

// CHECK: psb csync              // encoding: [0x3f,0x22,0x03,0xd5]
@@ -9,7 +16,6 @@ 
  msr pmblimitr_el1, x0

  msr pmbptr_el1, x0

  msr pmbsr_el1, x0

  msr pmbidr_el1, x0

  msr pmscr_el2, x0

  msr pmscr_el12, x0

  msr pmscr_el1, x0
@@ -18,11 +24,9 @@ 
  msr pmsfcr_el1, x0

  msr pmsevfr_el1, x0

  msr pmslatfr_el1, x0

  msr pmsidr_el1, x0

// CHECK:     msr PMBLIMITR_EL1, x0       // encoding: [0x00,0x9a,0x18,0xd5]

// CHECK:     msr PMBPTR_EL1, x0          // encoding: [0x20,0x9a,0x18,0xd5]

// CHECK:     msr PMBSR_EL1, x0           // encoding: [0x60,0x9a,0x18,0xd5]

// CHECK:     msr PMBIDR_EL1, x0          // encoding: [0xe0,0x9a,0x18,0xd5]

// CHECK:     msr PMSCR_EL2, x0           // encoding: [0x00,0x99,0x1c,0xd5]

// CHECK:     msr PMSCR_EL12, x0          // encoding: [0x00,0x99,0x1d,0xd5]

// CHECK:     msr PMSCR_EL1, x0           // encoding: [0x00,0x99,0x18,0xd5]
@@ -31,9 +35,6 @@ 
// CHECK:     msr PMSFCR_EL1, x0          // encoding: [0x80,0x99,0x18,0xd5]

// CHECK:     msr PMSEVFR_EL1, x0         // encoding: [0xa0,0x99,0x18,0xd5]

// CHECK:     msr PMSLATFR_EL1, x0        // encoding: [0xc0,0x99,0x18,0xd5]

// CHECK:     msr PMSIDR_EL1, x0          // encoding: [0xe0,0x99,0x18,0xd5]

// NO_SPE: error: expected writable system register or pstate

// NO_SPE: error: expected writable system register or pstate

// NO_SPE: error: expected writable system register or pstate

// NO_SPE: error: expected writable system register or pstate

// NO_SPE: error: expected writable system register or pstate
@@ -46,6 +47,15 @@ 
// NO_SPE: error: expected writable system register or pstate

// NO_SPE: error: expected writable system register or pstate





// Readonly system registers: writing to them gives an error

  msr pmbidr_el1, x0

  msr pmsidr_el1, x0

// ERROR: :[[@LINE-2]]:7: error: expected writable system register or pstate

// ERROR: :[[@LINE-2]]:7: error: expected writable system register or pstate

// NO_SPE: :[[@LINE-4]]:7: error: expected writable system register or pstate

// NO_SPE: :[[@LINE-4]]:7: error: expected writable system register or pstate



mrs x0, pmblimitr_el1

  mrs x0, pmbptr_el1

  mrs x0, pmbsr_el1

llvm/test/MC/AArch64/basic-a64-diagnostics.s

+6 −4
Original line number Diff line number Diff line
@@ -3375,10 +3375,12 @@ 
        msr spsel, #-1

        msr spsel #-1

        msr daifclr, #16

// CHECK-ERROR: [[@LINE-4]]:22: error: {{expected|immediate must be an}} integer in range [0, 15]

// CHECK-ERROR: [[@LINE-4]]:20: error: {{expected|immediate must be an}} integer in range [0, 15]

// CHECK-ERROR: [[@LINE-4]]:{{9|19}}: error: {{too few operands for instruction|expected comma before next operand|unexpected token in argument list}}

// CHECK-ERROR: [[@LINE-4]]:22: error: {{expected|immediate must be an}} integer in range [0, 15]

        msr CurrentEL, x12

// CHECK-ERROR: [[@LINE-5]]:22: error: {{expected|immediate must be an}} integer in range [0, 15]

// CHECK-ERROR: [[@LINE-5]]:20: error: {{expected|immediate must be an}} integer in range [0, 15]

// CHECK-ERROR: [[@LINE-5]]:{{9|19}}: error: {{too few operands for instruction|expected comma before next operand|unexpected token in argument list}}

// CHECK-ERROR: [[@LINE-5]]:22: error: {{expected|immediate must be an}} integer in range [0, 15]

// CHECK-ERROR: [[@LINE-5]]:13: error: expected writable system register or pstate



        sys #8, c1, c2, #7, x9

        sys #3, c16, c2, #3, x10

llvm/test/MC/AArch64/basic-a64-instructions.s

+1 −3
Original line number Diff line number Diff line 
// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+fp-armv8 < %s | FileCheck %s

// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+fp-armv8 %s | FileCheck %s

  .globl _func



// Check that the assembler can handle the documented syntax from the ARM ARM.
@@ -3804,7 +3804,6 @@ _func: 
	msr SPSel, x12

	msr NZCV, x12

	msr DAIF, x12

	msr CurrentEL, x12

	msr SPSR_irq, x12

	msr SPSR_abt, x12

	msr SPSR_und, x12
@@ -4058,7 +4057,6 @@ _func: 
// CHECK: msr      {{SPSel|SPSEL}}, x12                 // encoding: [0x0c,0x42,0x18,0xd5]

// CHECK: msr      {{nzcv|NZCV}}, x12                  // encoding: [0x0c,0x42,0x1b,0xd5]

// CHECK: msr      {{daif|DAIF}}, x12                  // encoding: [0x2c,0x42,0x1b,0xd5]

// CHECK: msr      {{CurrentEL|CURRENTEL}}, x12             // encoding: [0x4c,0x42,0x18,0xd5]

// CHECK: msr      {{SPSR_irq|SPSR_IRQ}}, x12              // encoding: [0x0c,0x43,0x1c,0xd5]

// CHECK: msr      {{SPSR_abt|SPSR_ABT}}, x12              // encoding: [0x2c,0x43,0x1c,0xd5]

// CHECK: msr      {{SPSR_und|SPSR_UND}}, x12              // encoding: [0x4c,0x43,0x1c,0xd5]