Commit a5bf48b8 authored by Nico Weber's avatar Nico Weber
Browse files

Revert "[X86] add mayRaiseFPException flag and FPCW registers for X87 instructions" 

This reverts commit a678677d.
It broke CodeGen/ms-inline-asm.c on most bots.
parent d889d1ef

llvm/lib/Target/X86/X86InstrFPStack.td

+24 −42
Original line number Diff line number Diff line
@@ -282,7 +282,7 @@ def _FI32m : FPI<0xDA, fp, (outs), (ins i32mem:$src), 
                  !strconcat("fi", asmstring, "{l}\t$src")>;

}



let Uses = [FPCW], mayRaiseFPException = 1 in {

let Defs = [FPSW], Uses = [FPCW] in {

// FPBinary_rr just defines pseudo-instructions, no need to set a scheduling

// resources.

let hasNoSchedulingInfo = 1 in {
@@ -307,7 +307,7 @@ let SchedRW = [WriteFDivLd] in { 
defm DIV : FPBinary<fdiv, MRM6m, "div">;

defm DIVR: FPBinary<fdiv, MRM7m, "divr", 0>;

}

} // Uses = [FPCW], mayRaiseFPException = 1

} // Defs = [FPSW]



class FPST0rInst<Format fp, string asm>

  : FPI<0xD8, fp, (outs), (ins RSTi:$op), asm>;
@@ -319,7 +319,7 @@ class FPrST0PInst<Format fp, string asm> 
// NOTE: GAS and apparently all other AT&T style assemblers have a broken notion

// of some of the 'reverse' forms of the fsub and fdiv instructions.  As such,

// we have to put some 'r's in and take them out of weird places.

let SchedRW = [WriteFAdd], Uses = [FPCW], mayRaiseFPException = 1 in {

let SchedRW = [WriteFAdd], Defs = [FPSW], Uses = [FPCW] in {

def ADD_FST0r   : FPST0rInst <MRM0r, "fadd\t{$op, %st|st, $op}">;

def ADD_FrST0   : FPrST0Inst <MRM0r, "fadd\t{%st, $op|$op, st}">;

def ADD_FPrST0  : FPrST0PInst<MRM0r, "faddp\t{%st, $op|$op, st}">;
@@ -330,16 +330,16 @@ def SUB_FST0r : FPST0rInst <MRM4r, "fsub\t{$op, %st|st, $op}">; 
def SUBR_FrST0  : FPrST0Inst <MRM4r, "fsub{|r}\t{%st, $op|$op, st}">;

def SUBR_FPrST0 : FPrST0PInst<MRM4r, "fsub{|r}p\t{%st, $op|$op, st}">;

} // SchedRW

let SchedRW = [WriteFCom], Uses = [FPCW], mayRaiseFPException = 1 in {

let SchedRW = [WriteFCom], Defs = [FPSW], Uses = [FPCW] in {

def COM_FST0r   : FPST0rInst <MRM2r, "fcom\t$op">;

def COMP_FST0r  : FPST0rInst <MRM3r, "fcomp\t$op">;

} // SchedRW

let SchedRW = [WriteFMul], Uses = [FPCW], mayRaiseFPException = 1 in {

let SchedRW = [WriteFMul], Defs = [FPSW], Uses = [FPCW] in {

def MUL_FST0r   : FPST0rInst <MRM1r, "fmul\t{$op, %st|st, $op}">;

def MUL_FrST0   : FPrST0Inst <MRM1r, "fmul\t{%st, $op|$op, st}">;

def MUL_FPrST0  : FPrST0PInst<MRM1r, "fmulp\t{%st, $op|$op, st}">;

} // SchedRW

let SchedRW = [WriteFDiv], Uses = [FPCW], mayRaiseFPException = 1 in {

let SchedRW = [WriteFDiv], Defs = [FPSW], Uses = [FPCW] in {

def DIVR_FST0r  : FPST0rInst <MRM7r, "fdivr\t{$op, %st|st, $op}">;

def DIV_FrST0   : FPrST0Inst <MRM7r, "fdiv{r}\t{%st, $op|$op, st}">;

def DIV_FPrST0  : FPrST0PInst<MRM7r, "fdiv{r}p\t{%st, $op|$op, st}">;
@@ -359,12 +359,13 @@ def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src), OneArgFPRW, 
def _F     : FPI<0xD9, fp, (outs), (ins), asmstring>;

}



let Defs = [FPSW], Uses = [FPCW] in {



let SchedRW = [WriteFSign] in {

defm CHS : FPUnary<fneg, MRM_E0, "fchs">;

defm ABS : FPUnary<fabs, MRM_E1, "fabs">;

}



let Uses = [FPCW], mayRaiseFPException = 1 in {

let SchedRW = [WriteFSqrt80] in

defm SQRT: FPUnary<fsqrt,MRM_FA, "fsqrt">;
@@ -377,11 +378,11 @@ def TST_Fp80 : FpI_<(outs), (ins RFP80:$src), OneArgFP, []>; 


def TST_F  : FPI<0xD9, MRM_E4, (outs), (ins), "ftst">;

} // SchedRW

} // Uses = [FPCW], mayRaiseFPException = 1

} // Defs = [FPSW]



// Versions of FP instructions that take a single memory operand.  Added for the

//   disassembler; remove as they are included with patterns elsewhere.

let SchedRW = [WriteFComLd], Uses = [FPCW], mayRaiseFPException = 1 in {

let SchedRW = [WriteFComLd], Defs = [FPSW], Uses = [FPCW] in {

def FCOM32m  : FPI<0xD8, MRM2m, (outs), (ins f32mem:$src), "fcom{s}\t$src">;

def FCOMP32m : FPI<0xD8, MRM3m, (outs), (ins f32mem:$src), "fcomp{s}\t$src">;
@@ -396,21 +397,14 @@ def FICOMP32m: FPI<0xDA, MRM3m, (outs), (ins i32mem:$src), "ficomp{l}\t$src">; 
} // SchedRW



let SchedRW = [WriteMicrocoded] in {

let Defs = [FPSW, FPCW] in {

def FLDENVm  : FPI<0xD9, MRM4m, (outs), (ins f32mem:$src), "fldenv\t$src">;

def FRSTORm  : FPI<0xDD, MRM4m, (outs), (ins f32mem:$dst), "frstor\t$dst">;

}



let Defs = [FPSW, FPCW], Uses = [FPSW, FPCW] in {

def FSTENVm  : FPI<0xD9, MRM6m, (outs), (ins f32mem:$dst), "fnstenv\t$dst">;

def FSAVEm   : FPI<0xDD, MRM6m, (outs), (ins f32mem:$dst), "fnsave\t$dst">;

}



let Uses = [FPSW] in

def FRSTORm  : FPI<0xDD, MRM4m, (outs), (ins f32mem:$dst), "frstor\t$dst">;

def FSAVEm   : FPI<0xDD, MRM6m, (outs), (ins f32mem:$dst), "fnsave\t$dst">;

def FNSTSWm  : FPI<0xDD, MRM7m, (outs), (ins i16mem:$dst), "fnstsw\t$dst">;



def FBLDm    : FPI<0xDF, MRM4m, (outs), (ins f80mem:$src), "fbld\t$src">;

let Uses = [FPCW] ,mayRaiseFPException = 1 in

def FBSTPm   : FPI<0xDF, MRM6m, (outs), (ins f80mem:$dst), "fbstp\t$dst">;

} // SchedRW
@@ -436,6 +430,7 @@ multiclass FPCMov<PatLeaf cc> { 
                                        Requires<[HasCMov]>;

}



let Defs = [FPSW] in {

let SchedRW = [WriteFCMOV] in {

let Uses = [EFLAGS], Constraints = "$src1 = $dst" in {

defm CMOVB  : FPCMov<X86_COND_B>;
@@ -469,7 +464,6 @@ def CMOVNP_F : FPI<0xDB, MRM3r, (outs), (ins RSTi:$op), 
} // Predicates = [HasCMov]

} // SchedRW



let mayRaiseFPException = 1 in {

// Floating point loads & stores.

let SchedRW = [WriteLoad], Uses = [FPCW] in {

let canFoldAsLoad = 1 in {
@@ -486,7 +480,6 @@ def LD_Fp64m80 : FpI_<(outs RFP80:$dst), (ins f64mem:$src), ZeroArgFP, 
                  [(set RFP80:$dst, (f80 (extloadf64 addr:$src)))]>;

def LD_Fp32m80 : FpI_<(outs RFP80:$dst), (ins f32mem:$src), ZeroArgFP,

                  [(set RFP80:$dst, (f80 (extloadf32 addr:$src)))]>;

let mayRaiseFPException = 0 in {

def ILD_Fp16m32: FpIf32<(outs RFP32:$dst), (ins i16mem:$src), ZeroArgFP,

                  [(set RFP32:$dst, (X86fild16 addr:$src))]>;

def ILD_Fp32m32: FpIf32<(outs RFP32:$dst), (ins i32mem:$src), ZeroArgFP,
@@ -505,7 +498,6 @@ def ILD_Fp32m80: FpI_<(outs RFP80:$dst), (ins i32mem:$src), ZeroArgFP, 
                  [(set RFP80:$dst, (X86fild32 addr:$src))]>;

def ILD_Fp64m80: FpI_<(outs RFP80:$dst), (ins i64mem:$src), ZeroArgFP,

                  [(set RFP80:$dst, (X86fild64 addr:$src))]>;

} // mayRaiseFPException = 0

} // SchedRW



let SchedRW = [WriteStore], Uses = [FPCW] in {
@@ -549,12 +541,10 @@ let mayLoad = 1, SchedRW = [WriteLoad], Uses = [FPCW] in { 
def LD_F32m   : FPI<0xD9, MRM0m, (outs), (ins f32mem:$src), "fld{s}\t$src">;

def LD_F64m   : FPI<0xDD, MRM0m, (outs), (ins f64mem:$src), "fld{l}\t$src">;

def LD_F80m   : FPI<0xDB, MRM5m, (outs), (ins f80mem:$src), "fld{t}\t$src">;

let mayRaiseFPException = 0 in {

def ILD_F16m  : FPI<0xDF, MRM0m, (outs), (ins i16mem:$src), "fild{s}\t$src">;

def ILD_F32m  : FPI<0xDB, MRM0m, (outs), (ins i32mem:$src), "fild{l}\t$src">;

def ILD_F64m  : FPI<0xDF, MRM5m, (outs), (ins i64mem:$src), "fild{ll}\t$src">;

}

}

let mayStore = 1, SchedRW = [WriteStore], Uses = [FPCW] in {

def ST_F32m   : FPI<0xD9, MRM2m, (outs), (ins f32mem:$dst), "fst{s}\t$dst">;

def ST_F64m   : FPI<0xDD, MRM2m, (outs), (ins f64mem:$dst), "fst{l}\t$dst">;
@@ -626,7 +616,7 @@ def LD_F0 : FPI<0xD9, MRM_EE, (outs), (ins), "fldz">; 
let SchedRW = [WriteFLD1], Uses = [FPCW] in

def LD_F1 : FPI<0xD9, MRM_E8, (outs), (ins), "fld1">;



let SchedRW = [WriteFLDC], Defs = [FPSW], Uses = [FPCW] in {

let SchedRW = [WriteFLDC], Uses = [FPCW] in {

def FLDL2T : I<0xD9, MRM_E9, (outs), (ins), "fldl2t", []>;

def FLDL2E : I<0xD9, MRM_EA, (outs), (ins), "fldl2e", []>;

def FLDPI : I<0xD9, MRM_EB, (outs), (ins), "fldpi", []>;
@@ -643,11 +633,11 @@ def UCOM_Fpr64 : FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP, 
def UCOM_Fpr80 : FpI_  <(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,

                        [(set FPSW, (trunc (X86cmp RFP80:$lhs, RFP80:$rhs)))]>;

} // SchedRW

} // mayRaiseFPException = 1

} // Defs = [FPSW]



let SchedRW = [WriteFCom], mayRaiseFPException = 1 in {

let SchedRW = [WriteFCom] in {

// CC = ST(0) cmp ST(i)

let Defs = [EFLAGS, FPCW], Uses = [FPCW] in {

let Defs = [EFLAGS, FPSW], Uses = [FPCW] in {

def UCOM_FpIr32: FpI_<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP,

                  [(set EFLAGS, (X86cmp RFP32:$lhs, RFP32:$rhs))]>,

                  Requires<[FPStackf32, HasCMov]>;
@@ -659,7 +649,7 @@ def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, 
                  Requires<[HasCMov]>;

}



let Uses = [ST0, FPCW] in {

let Defs = [FPSW], Uses = [ST0, FPCW] in {

def UCOM_Fr    : FPI<0xDD, MRM4r,    // FPSW = cmp ST(0) with ST(i)

                    (outs), (ins RSTi:$reg), "fucom\t$reg">;

def UCOM_FPr   : FPI<0xDD, MRM5r,    // FPSW = cmp ST(0) with ST(i), pop
@@ -683,7 +673,7 @@ def COM_FIPr : FPI<0xDF, MRM6r, (outs), (ins RSTi:$reg), 


// Floating point flag ops.

let SchedRW = [WriteALU] in {

let Defs = [AX, FPSW], Uses = [FPSW] in

let Defs = [AX], Uses = [FPSW] in

def FNSTSW16r : I<0xDF, MRM_E0,                  // AX = fp flags

                  (outs), (ins), "fnstsw\t{%ax|ax}",

                  [(set AX, (X86fp_stsw FPSW))]>;
@@ -699,33 +689,31 @@ def FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16] 


// FPU control instructions

let SchedRW = [WriteMicrocoded] in {

let Defs = [FPSW] in {

def FNINIT : I<0xDB, MRM_E3, (outs), (ins), "fninit", []>;

def FFREE : FPI<0xDD, MRM0r, (outs), (ins RSTi:$reg), "ffree\t$reg">;

def FFREEP : FPI<0xDF, MRM0r, (outs), (ins RSTi:$reg), "ffreep\t$reg">;



let Defs = [FPSW, FPCW] in

def FNINIT : I<0xDB, MRM_E3, (outs), (ins), "fninit", []>;

// Clear exceptions

let Defs = [FPSW] in

def FNCLEX : I<0xDB, MRM_E2, (outs), (ins), "fnclex", []>;

} // Defs = [FPSW]

} // SchedRW



// Operand-less floating-point instructions for the disassembler.

let Defs = [FPSW] in

def FNOP : I<0xD9, MRM_D0, (outs), (ins), "fnop", []>, Sched<[WriteNop]>;



let SchedRW = [WriteMicrocoded] in {

let Defs = [FPSW] in {

def WAIT : I<0x9B, RawFrm, (outs), (ins), "wait", []>;

def FXAM : I<0xD9, MRM_E5, (outs), (ins), "fxam", []>;

def FDECSTP : I<0xD9, MRM_F6, (outs), (ins), "fdecstp", []>;

def FINCSTP : I<0xD9, MRM_F7, (outs), (ins), "fincstp", []>;

let Uses = [FPCW], mayRaiseFPException = 1 in {

def F2XM1 : I<0xD9, MRM_F0, (outs), (ins), "f2xm1", []>;

def FYL2X : I<0xD9, MRM_F1, (outs), (ins), "fyl2x", []>;

def FPTAN : I<0xD9, MRM_F2, (outs), (ins), "fptan", []>;

def FPATAN : I<0xD9, MRM_F3, (outs), (ins), "fpatan", []>;

def FXTRACT : I<0xD9, MRM_F4, (outs), (ins), "fxtract", []>;

def FPREM1 : I<0xD9, MRM_F5, (outs), (ins), "fprem1", []>;

def FDECSTP : I<0xD9, MRM_F6, (outs), (ins), "fdecstp", []>;

def FINCSTP : I<0xD9, MRM_F7, (outs), (ins), "fincstp", []>;

def FPREM : I<0xD9, MRM_F8, (outs), (ins), "fprem", []>;

def FYL2XP1 : I<0xD9, MRM_F9, (outs), (ins), "fyl2xp1", []>;

def FSIN : I<0xD9, MRM_FE, (outs), (ins), "fsin", []>;
@@ -734,26 +722,20 @@ def FSINCOS : I<0xD9, MRM_FB, (outs), (ins), "fsincos", []>; 
def FRNDINT : I<0xD9, MRM_FC, (outs), (ins), "frndint", []>;

def FSCALE : I<0xD9, MRM_FD, (outs), (ins), "fscale", []>;

def FCOMPP : I<0xDE, MRM_D9, (outs), (ins), "fcompp", []>;

} // Uses = [FPCW], mayRaiseFPException = 1

} // Defs = [FPSW]



let Uses = [FPSW, FPCW] in {

def FXSAVE : I<0xAE, MRM0m, (outs), (ins opaquemem:$dst),

             "fxsave\t$dst", [(int_x86_fxsave addr:$dst)]>, TB,

             Requires<[HasFXSR]>;

def FXSAVE64 : RI<0xAE, MRM0m, (outs), (ins opaquemem:$dst),

               "fxsave64\t$dst", [(int_x86_fxsave64 addr:$dst)]>,

               TB, Requires<[HasFXSR, In64BitMode]>;

} // Uses = [FPSW, FPCW]



let Defs = [FPSW, FPCW] in {

def FXRSTOR : I<0xAE, MRM1m, (outs), (ins opaquemem:$src),

              "fxrstor\t$src", [(int_x86_fxrstor addr:$src)]>,

              TB, Requires<[HasFXSR]>;

def FXRSTOR64 : RI<0xAE, MRM1m, (outs), (ins opaquemem:$src),

                "fxrstor64\t$src", [(int_x86_fxrstor64 addr:$src)]>,

                TB, Requires<[HasFXSR, In64BitMode]>;

} // Defs = [FPSW, FPCW]

} // SchedRW



//===----------------------------------------------------------------------===//

llvm/lib/Target/X86/X86InstrFormats.td

+1 −4
Original line number Diff line number Diff line
@@ -442,15 +442,12 @@ class Ii32PCRel<bits<8> o, Format f, dag outs, dag ins, string asm, 
// FPStack Instruction Templates:

// FPI - Floating Point Instruction template.

class FPI<bits<8> o, Format F, dag outs, dag ins, string asm>

  : I<o, F, outs, ins, asm, []> {

  let Defs = [FPSW];

}

  : I<o, F, outs, ins, asm, []> {}



// FpI_ - Floating Point Pseudo Instruction template. Not Predicated.

class FpI_<dag outs, dag ins, FPFormat fp, list<dag> pattern>

  : PseudoI<outs, ins, pattern> {

  let FPForm = fp;

  let Defs = [FPSW];

}



// Templates for instructions that use a 16- or 32-bit segmented address as

llvm/test/CodeGen/X86/x87-reg-usage.mir

deleted100644 → 0
+0 −248
Original line number Diff line number Diff line 
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=x86-64 -mattr=+x87 -mattr=-sse -run-pass none -o - %s | FileCheck %s

# This test ensures that the MIR parser parses the x87 fpcw and fpcw regs



--- |

  declare float @llvm.sqrt.f32(float)



  define void @f1(float* %a, float* %b) {

    %1 = load float, float* %a, align 4

    %2 = load float, float* %b, align 4

    %sub = fsub float %1, %2

    store float %sub, float* %a, align 4

    ret void

  }



  define void @f2(double* %a, double* %b) {

    %1 = load double, double* %a, align 8

    %2 = load double, double* %b, align 8

    %add = fadd double %1, %2

    store double %add, double* %a, align 8

    ret void

  }



  define void @f3(x86_fp80* %a, x86_fp80* %b) {

    %1 = load x86_fp80, x86_fp80* %a, align 16

    %2 = load x86_fp80, x86_fp80* %b, align 16

    %mul = fmul x86_fp80 %1, %2

    store x86_fp80 %mul, x86_fp80* %a, align 16

    ret void

  }



  define void @f4(float* %a, float* %b) {

    %1 = load float, float* %a, align 4

    %2 = load float, float* %b, align 4

    %div = fdiv float %1, %2

    store float %div, float* %a, align 4

    ret void

  }



  define void @f5(float* %val, double* %ret) {

    %1 = load float, float* %val, align 4

    %res = fpext float %1 to double

    store double %res, double* %ret, align 8

    ret void

  }



  define void @f6(double* %val, float* %ret) {

    %1 = load double, double* %val, align 8

    %res = fptrunc double %1 to float

    store float %res, float* %ret, align 4

    ret void

  }



  define void @f7(float* %a) {

    %1 = load float, float* %a, align 4

    %res = call float @llvm.sqrt.f32(float %1)

    store float %res, float* %a, align 4

    ret void

  }







...

---

name:            f1

alignment:       16

tracksRegLiveness: true

liveins:

  - { reg: '$rdi' }

  - { reg: '$rsi' }

frameInfo:

  maxAlignment:    1

machineFunctionInfo: {}

body:             |

  bb.0 (%ir-block.0):

    liveins: $rdi, $rsi



    ; CHECK-LABEL: name: f1

    ; CHECK: liveins: $rdi, $rsi

    ; CHECK: renamable $fp0 = LD_Fp32m renamable $rdi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 4 from %ir.a)

    ; CHECK: renamable $fp0 = SUB_Fp32m killed renamable $fp0, killed renamable $rsi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 4 from %ir.b)

    ; CHECK: ST_Fp32m killed renamable $rdi, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store 4 into %ir.a)

    ; CHECK: RET 0

    renamable $fp0 = LD_Fp32m renamable $rdi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 4 from %ir.a)

    renamable $fp0 = SUB_Fp32m killed renamable $fp0, killed renamable $rsi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 4 from %ir.b)

    ST_Fp32m killed renamable $rdi, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store 4 into %ir.a)

    RET 0



...

---

name:            f2

alignment:       16

tracksRegLiveness: true

liveins:

  - { reg: '$rdi' }

  - { reg: '$rsi' }

frameInfo:

  maxAlignment:    1

machineFunctionInfo: {}

body:             |

  bb.0 (%ir-block.0):

    liveins: $rdi, $rsi



    ; CHECK-LABEL: name: f2

    ; CHECK: liveins: $rdi, $rsi

    ; CHECK: renamable $fp0 = LD_Fp64m renamable $rdi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 8 from %ir.a)

    ; CHECK: renamable $fp0 = ADD_Fp64m killed renamable $fp0, killed renamable $rsi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 8 from %ir.b)

    ; CHECK: ST_Fp64m killed renamable $rdi, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store 8 into %ir.a)

    ; CHECK: RET 0

    renamable $fp0 = LD_Fp64m renamable $rdi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 8 from %ir.a)

    renamable $fp0 = ADD_Fp64m killed renamable $fp0, killed renamable $rsi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 8 from %ir.b)

    ST_Fp64m killed renamable $rdi, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store 8 into %ir.a)

    RET 0



...

---

name:            f3

alignment:       16

tracksRegLiveness: true

liveins:

  - { reg: '$rdi' }

  - { reg: '$rsi' }

frameInfo:

  maxAlignment:    1

machineFunctionInfo: {}

body:             |

  bb.0 (%ir-block.0):

    liveins: $rdi, $rsi



    ; CHECK-LABEL: name: f3

    ; CHECK: liveins: $rdi, $rsi

    ; CHECK: renamable $fp0 = LD_Fp80m renamable $rdi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 10 from %ir.a, align 16)

    ; CHECK: renamable $fp1 = LD_Fp80m killed renamable $rsi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 10 from %ir.b, align 16)

    ; CHECK: renamable $fp0 = MUL_Fp80 killed renamable $fp0, killed renamable $fp1, implicit-def dead $fpsw, implicit $fpcw

    ; CHECK: ST_FpP80m killed renamable $rdi, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store 10 into %ir.a, align 16)

    ; CHECK: RET 0

    renamable $fp0 = LD_Fp80m renamable $rdi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 10 from %ir.a, align 16)

    renamable $fp1 = LD_Fp80m killed renamable $rsi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 10 from %ir.b, align 16)

    renamable $fp0 = MUL_Fp80 killed renamable $fp0, killed renamable $fp1, implicit-def dead $fpsw, implicit $fpcw

    ST_FpP80m killed renamable $rdi, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store 10 into %ir.a, align 16)

    RET 0



...

---

name:            f4

alignment:       16

tracksRegLiveness: true

liveins:

  - { reg: '$rdi' }

  - { reg: '$rsi' }

frameInfo:

  maxAlignment:    1

machineFunctionInfo: {}

body:             |

  bb.0 (%ir-block.0):

    liveins: $rdi, $rsi



    ; CHECK-LABEL: name: f4

    ; CHECK: liveins: $rdi, $rsi

    ; CHECK: renamable $fp0 = LD_Fp32m renamable $rdi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 4 from %ir.a)

    ; CHECK: renamable $fp0 = DIV_Fp32m killed renamable $fp0, killed renamable $rsi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 4 from %ir.b)

    ; CHECK: ST_Fp32m killed renamable $rdi, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store 4 into %ir.a)

    ; CHECK: RET 0

    renamable $fp0 = LD_Fp32m renamable $rdi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 4 from %ir.a)

    renamable $fp0 = DIV_Fp32m killed renamable $fp0, killed renamable $rsi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 4 from %ir.b)

    ST_Fp32m killed renamable $rdi, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store 4 into %ir.a)

    RET 0



...

---

name:            f5

alignment:       16

tracksRegLiveness: true

liveins:

  - { reg: '$rdi' }

  - { reg: '$rsi' }

frameInfo:

  maxAlignment:    1

machineFunctionInfo: {}

body:             |

  bb.0 (%ir-block.0):

    liveins: $rdi, $rsi



    ; CHECK-LABEL: name: f5

    ; CHECK: liveins: $rdi, $rsi

    ; CHECK: renamable $fp0 = LD_Fp32m64 killed renamable $rdi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 4 from %ir.val)

    ; CHECK: ST_Fp64m killed renamable $rsi, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store 8 into %ir.ret)

    ; CHECK: RET 0

    renamable $fp0 = LD_Fp32m64 killed renamable $rdi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 4 from %ir.val)

    ST_Fp64m killed renamable $rsi, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store 8 into %ir.ret)

    RET 0



...

---

name:            f6

alignment:       16

tracksRegLiveness: true

liveins:

  - { reg: '$rdi' }

  - { reg: '$rsi' }

frameInfo:

  maxAlignment:    4

stack:

  - { id: 0, size: 4, alignment: 4 }

machineFunctionInfo: {}

body:             |

  bb.0 (%ir-block.0):

    liveins: $rdi, $rsi



    ; CHECK-LABEL: name: f6

    ; CHECK: liveins: $rdi, $rsi

    ; CHECK: renamable $fp0 = LD_Fp64m killed renamable $rdi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 8 from %ir.val)

    ; CHECK: ST_Fp64m32 %stack.0, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store 4 into %stack.0)

    ; CHECK: renamable $fp0 = LD_Fp32m %stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 4 from %stack.0)

    ; CHECK: ST_Fp32m killed renamable $rsi, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store 4 into %ir.ret)

    ; CHECK: RET 0

    renamable $fp0 = LD_Fp64m killed renamable $rdi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 8 from %ir.val)

    ST_Fp64m32 %stack.0, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store 4 into %stack.0)

    renamable $fp0 = LD_Fp32m %stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 4 from %stack.0)

    ST_Fp32m killed renamable $rsi, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store 4 into %ir.ret)

    RET 0



...

---

name:            f7

alignment:       16

tracksRegLiveness: true

liveins:

  - { reg: '$rdi' }

frameInfo:

  maxAlignment:    1

machineFunctionInfo: {}

body:             |

  bb.0 (%ir-block.0):

    liveins: $rdi



    ; CHECK-LABEL: name: f7

    ; CHECK: liveins: $rdi

    ; CHECK: renamable $fp0 = LD_Fp32m renamable $rdi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 4 from %ir.a)

    ; CHECK: renamable $fp0 = SQRT_Fp32 killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw

    ; CHECK: ST_Fp32m killed renamable $rdi, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store 4 into %ir.a)

    ; CHECK: RET 0

    renamable $fp0 = LD_Fp32m renamable $rdi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 4 from %ir.a)

    renamable $fp0 = SQRT_Fp32 killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw

    ST_Fp32m killed renamable $rdi, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store 4 into %ir.a)

    RET 0



...