Commit a5a4a47d authored by Huihui Zhang's avatar Huihui Zhang
Browse files

[AArch64] Fix data race on RegisterBank initialization. 

Summary:
The initialization of RegisterBank needs to be done only once. The
logic of AlreadyInit has a data race, use llvm::call_once instead.

This issue was identified through thread sanitizer.

Reviewers: efriedma, apazos, qcolombet, dsanders

Reviewed By: efriedma

Subscribers: arsenm, kristof.beyls, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D73587
parent b4c911ec

llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp

+91 −88
Original line number Diff line number Diff line
@@ -38,15 +38,14 @@ using namespace llvm; 


AArch64RegisterBankInfo::AArch64RegisterBankInfo(const TargetRegisterInfo &TRI)

    : AArch64GenRegisterBankInfo() {

  static bool AlreadyInit = false;

  static llvm::once_flag InitializeRegisterBankFlag;



  static auto InitializeRegisterBankOnce = [this](const auto &TRI) {

    // We have only one set of register banks, whatever the subtarget

    // is. Therefore, the initialization of the RegBanks table should be

    // done only once. Indeed the table of all register banks

    // (AArch64::RegBanks) is unique in the compiler. At some point, it

    // will get tablegen'ed and the whole constructor becomes empty.

  if (AlreadyInit)

    return;

  AlreadyInit = true;



    const RegisterBank &RBGPR = getRegBank(AArch64::GPRRegBankID);

    (void)RBGPR;
@@ -60,7 +59,8 @@ AArch64RegisterBankInfo::AArch64RegisterBankInfo(const TargetRegisterInfo &TRI) 


    const RegisterBank &RBCCR = getRegBank(AArch64::CCRegBankID);

    (void)RBCCR;

  assert(&AArch64::CCRegBank == &RBCCR && "The order in RegBanks is messed up");

    assert(&AArch64::CCRegBank == &RBCCR &&

           "The order in RegBanks is messed up");



    // The GPR register bank is fully defined by all the registers in

    // GR64all + its subclasses.
@@ -199,6 +199,9 @@ AArch64RegisterBankInfo::AArch64RegisterBankInfo(const TargetRegisterInfo &TRI) 
    CHECK_VALUEMAP_FPEXT(128, 64);



    assert(verify(TRI) && "Invalid register bank information");

  };



  llvm::call_once(InitializeRegisterBankFlag, InitializeRegisterBankOnce, TRI);

}



unsigned AArch64RegisterBankInfo::copyCost(const RegisterBank &A,