Commit a249eb8c authored by Tom Stellard's avatar Tom Stellard
Browse files

Merging r284620: 

------------------------------------------------------------------------
r284620 | simon.dardis | 2016-10-19 10:50:52 -0700 (Wed, 19 Oct 2016) | 14 lines

[mips][msa] Range check MSA intrinsics with immediates

This patch teaches clang to range check immediates for MIPS MSA instrinsics.
This checking is done strictly in comparison to some existing GCC
implementations. E.g. msa_andvi_b(var, 257) does not result in andvi $wX, 1.
Similarily msa_ldi_b takes a range of -128 to 127.

As part of this effort, correct the existing MSA test as it has both illegal
types and immediates.

Reviewers: vkalintiris

Differential Revision: https://reviews.llvm.org/D25017

------------------------------------------------------------------------

llvm-svn: 288109
parent 8751bb02

clang/include/clang/Basic/DiagnosticSemaKinds.td

+2 −0
Original line number Diff line number Diff line
@@ -7621,6 +7621,8 @@ def err_invalid_neon_type_code : Error< 
  "incompatible constant for this __builtin_neon function">; 

def err_argument_invalid_range : Error<

  "argument should be a value from %0 to %1">;

def err_argument_not_multiple : Error<

  "argument should be a multiple of %0">;

def warn_neon_vector_initializer_non_portable : Warning<

  "vector initializers are not compatible with NEON intrinsics in big endian "

  "mode">, InGroup<DiagGroup<"nonportable-vector-initialization">>;

clang/include/clang/Sema/Sema.h

+2 −0
Original line number Diff line number Diff line
@@ -9417,6 +9417,8 @@ private: 
                              llvm::APSInt &Result);

  bool SemaBuiltinConstantArgRange(CallExpr *TheCall, int ArgNum,

                                   int Low, int High);

  bool SemaBuiltinConstantArgMultiple(CallExpr *TheCall, int ArgNum,

                                      unsigned Multiple);

  bool SemaBuiltinARMSpecialReg(unsigned BuiltinID, CallExpr *TheCall,

                                int ArgNum, unsigned ExpectedFieldNum,

                                bool AllowName);

clang/lib/Sema/SemaChecking.cpp

+194 −4
Original line number Diff line number Diff line
@@ -1454,8 +1454,17 @@ bool Sema::CheckAArch64BuiltinFunctionCall(unsigned BuiltinID, 
  return SemaBuiltinConstantArgRange(TheCall, i, l, u + l);

}



// CheckMipsBuiltinFunctionCall - Checks the constant value passed to the

// intrinsic is correct. The switch statement is ordered by DSP, MSA. The

// ordering for DSP is unspecified. MSA is ordered by the data format used

// by the underlying instruction i.e., df/m, df/n and then by size.

//

// FIXME: The size tests here should instead be tablegen'd along with the

//        definitions from include/clang/Basic/BuiltinsMips.def.

// FIXME: GCC is strict on signedness for some of these intrinsics, we should

//        be too.

bool Sema::CheckMipsBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall) {

  unsigned i = 0, l = 0, u = 0;

  unsigned i = 0, l = 0, u = 0, m = 0;

  switch (BuiltinID) {

  default: return false;

  case Mips::BI__builtin_mips_wrdsp: i = 1; l = 0; u = 63; break;
@@ -1465,9 +1474,168 @@ bool Sema::CheckMipsBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall) { 
  case Mips::BI__builtin_mips_precr_sra_ph_w: i = 2; l = 0; u = 31; break;

  case Mips::BI__builtin_mips_precr_sra_r_ph_w: i = 2; l = 0; u = 31; break;

  case Mips::BI__builtin_mips_prepend: i = 2; l = 0; u = 31; break;

  }



  // MSA instrinsics. Instructions (which the intrinsics maps to) which use the

  // df/m field.

  // These intrinsics take an unsigned 3 bit immediate.

  case Mips::BI__builtin_msa_bclri_b:

  case Mips::BI__builtin_msa_bnegi_b:

  case Mips::BI__builtin_msa_bseti_b:

  case Mips::BI__builtin_msa_sat_s_b:

  case Mips::BI__builtin_msa_sat_u_b:

  case Mips::BI__builtin_msa_slli_b:

  case Mips::BI__builtin_msa_srai_b:

  case Mips::BI__builtin_msa_srari_b:

  case Mips::BI__builtin_msa_srli_b:

  case Mips::BI__builtin_msa_srlri_b: i = 1; l = 0; u = 7; break;

  case Mips::BI__builtin_msa_binsli_b:

  case Mips::BI__builtin_msa_binsri_b: i = 2; l = 0; u = 7; break;

  // These intrinsics take an unsigned 4 bit immediate.

  case Mips::BI__builtin_msa_bclri_h:

  case Mips::BI__builtin_msa_bnegi_h:

  case Mips::BI__builtin_msa_bseti_h:

  case Mips::BI__builtin_msa_sat_s_h:

  case Mips::BI__builtin_msa_sat_u_h:

  case Mips::BI__builtin_msa_slli_h:

  case Mips::BI__builtin_msa_srai_h:

  case Mips::BI__builtin_msa_srari_h:

  case Mips::BI__builtin_msa_srli_h:

  case Mips::BI__builtin_msa_srlri_h: i = 1; l = 0; u = 15; break;

  case Mips::BI__builtin_msa_binsli_h:

  case Mips::BI__builtin_msa_binsri_h: i = 2; l = 0; u = 15; break;

  // These intrinsics take an unsigned 5 bit immedate.

  // The first block of intrinsics actually have an unsigned 5 bit field,

  // not a df/n field.

  case Mips::BI__builtin_msa_clei_u_b:

  case Mips::BI__builtin_msa_clei_u_h:

  case Mips::BI__builtin_msa_clei_u_w:

  case Mips::BI__builtin_msa_clei_u_d:

  case Mips::BI__builtin_msa_clti_u_b:

  case Mips::BI__builtin_msa_clti_u_h:

  case Mips::BI__builtin_msa_clti_u_w:

  case Mips::BI__builtin_msa_clti_u_d:

  case Mips::BI__builtin_msa_maxi_u_b:

  case Mips::BI__builtin_msa_maxi_u_h:

  case Mips::BI__builtin_msa_maxi_u_w:

  case Mips::BI__builtin_msa_maxi_u_d:

  case Mips::BI__builtin_msa_mini_u_b:

  case Mips::BI__builtin_msa_mini_u_h:

  case Mips::BI__builtin_msa_mini_u_w:

  case Mips::BI__builtin_msa_mini_u_d:

  case Mips::BI__builtin_msa_addvi_b:

  case Mips::BI__builtin_msa_addvi_h:

  case Mips::BI__builtin_msa_addvi_w:

  case Mips::BI__builtin_msa_addvi_d:

  case Mips::BI__builtin_msa_bclri_w:

  case Mips::BI__builtin_msa_bnegi_w:

  case Mips::BI__builtin_msa_bseti_w:

  case Mips::BI__builtin_msa_sat_s_w:

  case Mips::BI__builtin_msa_sat_u_w:

  case Mips::BI__builtin_msa_slli_w:

  case Mips::BI__builtin_msa_srai_w:

  case Mips::BI__builtin_msa_srari_w:

  case Mips::BI__builtin_msa_srli_w:

  case Mips::BI__builtin_msa_srlri_w:

  case Mips::BI__builtin_msa_subvi_b:

  case Mips::BI__builtin_msa_subvi_h:

  case Mips::BI__builtin_msa_subvi_w:

  case Mips::BI__builtin_msa_subvi_d: i = 1; l = 0; u = 31; break;

  case Mips::BI__builtin_msa_binsli_w:

  case Mips::BI__builtin_msa_binsri_w: i = 2; l = 0; u = 31; break;

  // These intrinsics take an unsigned 6 bit immediate.

  case Mips::BI__builtin_msa_bclri_d:

  case Mips::BI__builtin_msa_bnegi_d:

  case Mips::BI__builtin_msa_bseti_d:

  case Mips::BI__builtin_msa_sat_s_d:

  case Mips::BI__builtin_msa_sat_u_d:

  case Mips::BI__builtin_msa_slli_d:

  case Mips::BI__builtin_msa_srai_d:

  case Mips::BI__builtin_msa_srari_d:

  case Mips::BI__builtin_msa_srli_d:

  case Mips::BI__builtin_msa_srlri_d: i = 1; l = 0; u = 63; break;

  case Mips::BI__builtin_msa_binsli_d:

  case Mips::BI__builtin_msa_binsri_d: i = 2; l = 0; u = 63; break;

  // These intrinsics take a signed 5 bit immediate.

  case Mips::BI__builtin_msa_ceqi_b:

  case Mips::BI__builtin_msa_ceqi_h:

  case Mips::BI__builtin_msa_ceqi_w:

  case Mips::BI__builtin_msa_ceqi_d:

  case Mips::BI__builtin_msa_clti_s_b:

  case Mips::BI__builtin_msa_clti_s_h:

  case Mips::BI__builtin_msa_clti_s_w:

  case Mips::BI__builtin_msa_clti_s_d:

  case Mips::BI__builtin_msa_clei_s_b:

  case Mips::BI__builtin_msa_clei_s_h:

  case Mips::BI__builtin_msa_clei_s_w:

  case Mips::BI__builtin_msa_clei_s_d:

  case Mips::BI__builtin_msa_maxi_s_b:

  case Mips::BI__builtin_msa_maxi_s_h:

  case Mips::BI__builtin_msa_maxi_s_w:

  case Mips::BI__builtin_msa_maxi_s_d:

  case Mips::BI__builtin_msa_mini_s_b:

  case Mips::BI__builtin_msa_mini_s_h:

  case Mips::BI__builtin_msa_mini_s_w:

  case Mips::BI__builtin_msa_mini_s_d: i = 1; l = -16; u = 15; break;

  // These intrinsics take an unsigned 8 bit immediate.

  case Mips::BI__builtin_msa_andi_b:

  case Mips::BI__builtin_msa_nori_b:

  case Mips::BI__builtin_msa_ori_b:

  case Mips::BI__builtin_msa_shf_b:

  case Mips::BI__builtin_msa_shf_h:

  case Mips::BI__builtin_msa_shf_w:

  case Mips::BI__builtin_msa_xori_b: i = 1; l = 0; u = 255; break;

  case Mips::BI__builtin_msa_bseli_b:

  case Mips::BI__builtin_msa_bmnzi_b:

  case Mips::BI__builtin_msa_bmzi_b: i = 2; l = 0; u = 255; break;

  // df/n format

  // These intrinsics take an unsigned 4 bit immediate.

  case Mips::BI__builtin_msa_copy_s_b:

  case Mips::BI__builtin_msa_copy_u_b:

  case Mips::BI__builtin_msa_insve_b:

  case Mips::BI__builtin_msa_splati_b: i = 1; l = 0; u = 15; break;

  case Mips::BI__builtin_msa_sld_b:

  case Mips::BI__builtin_msa_sldi_b: i = 2; l = 0; u = 15; break;

  // These intrinsics take an unsigned 3 bit immediate.

  case Mips::BI__builtin_msa_copy_s_h:

  case Mips::BI__builtin_msa_copy_u_h:

  case Mips::BI__builtin_msa_insve_h:

  case Mips::BI__builtin_msa_splati_h: i = 1; l = 0; u = 7; break;

  case Mips::BI__builtin_msa_sld_h:

  case Mips::BI__builtin_msa_sldi_h: i = 2; l = 0; u = 7; break;

  // These intrinsics take an unsigned 2 bit immediate.

  case Mips::BI__builtin_msa_copy_s_w:

  case Mips::BI__builtin_msa_copy_u_w:

  case Mips::BI__builtin_msa_insve_w:

  case Mips::BI__builtin_msa_splati_w: i = 1; l = 0; u = 3; break;

  case Mips::BI__builtin_msa_sld_w:

  case Mips::BI__builtin_msa_sldi_w: i = 2; l = 0; u = 3; break;

  // These intrinsics take an unsigned 1 bit immediate.

  case Mips::BI__builtin_msa_copy_s_d:

  case Mips::BI__builtin_msa_copy_u_d:

  case Mips::BI__builtin_msa_insve_d:

  case Mips::BI__builtin_msa_splati_d: i = 1; l = 0; u = 1; break;

  case Mips::BI__builtin_msa_sld_d:

  case Mips::BI__builtin_msa_sldi_d: i = 2; l = 0; u = 1; break;

  // Memory offsets and immediate loads.

  // These intrinsics take a signed 10 bit immediate.

  case Mips::BI__builtin_msa_ldi_b: i = 0; l = -128; u = 127; break;

  case Mips::BI__builtin_msa_ldi_h:

  case Mips::BI__builtin_msa_ldi_w:

  case Mips::BI__builtin_msa_ldi_d: i = 0; l = -512; u = 511; break;

  case Mips::BI__builtin_msa_ld_b: i = 1; l = -512; u = 511; m = 16; break;

  case Mips::BI__builtin_msa_ld_h: i = 1; l = -1024; u = 1022; m = 16; break;

  case Mips::BI__builtin_msa_ld_w: i = 1; l = -2048; u = 2044; m = 16; break;

  case Mips::BI__builtin_msa_ld_d: i = 1; l = -4096; u = 4088; m = 16; break;

  case Mips::BI__builtin_msa_st_b: i = 2; l = -512; u = 511; m = 16; break;

  case Mips::BI__builtin_msa_st_h: i = 2; l = -1024; u = 1022; m = 16; break;

  case Mips::BI__builtin_msa_st_w: i = 2; l = -2048; u = 2044; m = 16; break;

  case Mips::BI__builtin_msa_st_d: i = 2; l = -4096; u = 4088; m = 16; break;

  }



  if (!m)

    return SemaBuiltinConstantArgRange(TheCall, i, l, u);



  return SemaBuiltinConstantArgRange(TheCall, i, l, u) ||

         SemaBuiltinConstantArgMultiple(TheCall, i, m);

}



bool Sema::CheckPPCBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall) {
@@ -3605,6 +3773,28 @@ bool Sema::SemaBuiltinConstantArgRange(CallExpr *TheCall, int ArgNum, 
  return false;

}



/// SemaBuiltinConstantArgMultiple - Handle a check if argument ArgNum of CallExpr

/// TheCall is a constant expression is a multiple of Num..

bool Sema::SemaBuiltinConstantArgMultiple(CallExpr *TheCall, int ArgNum,

                                          unsigned Num) {

  llvm::APSInt Result;



  // We can't check the value of a dependent argument.

  Expr *Arg = TheCall->getArg(ArgNum);

  if (Arg->isTypeDependent() || Arg->isValueDependent())

    return false;



  // Check constant-ness first.

  if (SemaBuiltinConstantArg(TheCall, ArgNum, Result))

    return true;



  if (Result.getSExtValue() % Num != 0)

    return Diag(TheCall->getLocStart(), diag::err_argument_not_multiple)

      << Num << Arg->getSourceRange();



  return false;

}



/// SemaBuiltinARMSpecialReg - Handle a check if argument ArgNum of CallExpr

/// TheCall is an ARM/AArch64 special register string literal.

bool Sema::SemaBuiltinARMSpecialReg(unsigned BuiltinID, CallExpr *TheCall,

clang/test/CodeGen/builtins-mips-msa-error.c

0 → 100644
+421 −0

File added.

Preview size limit exceeded, changes collapsed.

clang/test/CodeGen/builtins-mips-msa.c

+52 −52
Original line number Diff line number Diff line
@@ -138,8 +138,8 @@ void test(void) { 
  v4i32_r = __msa_bclr_w(v4i32_a, v4i32_b); // CHECK: call <4  x i32> @llvm.mips.bclr.w(

  v2i64_r = __msa_bclr_d(v2i64_a, v2i64_b); // CHECK: call <2  x i64> @llvm.mips.bclr.d(



  v16i8_r = __msa_bclri_b(v16i8_a, 25); // CHECK: call <16 x i8>  @llvm.mips.bclri.b(

  v8i16_r = __msa_bclri_h(v8i16_a, 25); // CHECK: call <8  x i16> @llvm.mips.bclri.h(

  v16i8_r = __msa_bclri_b(v16i8_a, 3); // CHECK: call <16 x i8>  @llvm.mips.bclri.b(

  v8i16_r = __msa_bclri_h(v8i16_a, 8); // CHECK: call <8  x i16> @llvm.mips.bclri.h(

  v4i32_r = __msa_bclri_w(v4i32_a, 25); // CHECK: call <4  x i32> @llvm.mips.bclri.w(

  v2i64_r = __msa_bclri_d(v2i64_a, 25); // CHECK: call <2  x i64> @llvm.mips.bclri.d(
@@ -148,8 +148,8 @@ void test(void) { 
  v4i32_r = __msa_binsl_w(v4i32_r, v4i32_a, v4i32_b); // CHECK: call <4  x i32> @llvm.mips.binsl.w(

  v2i64_r = __msa_binsl_d(v2i64_r, v2i64_a, v2i64_b); // CHECK: call <2  x i64> @llvm.mips.binsl.d(



  v16i8_r = __msa_binsli_b(v16i8_r, v16i8_a, 25); // CHECK: call <16 x i8>  @llvm.mips.binsli.b(

  v8i16_r = __msa_binsli_h(v8i16_r, v8i16_a, 25); // CHECK: call <8  x i16> @llvm.mips.binsli.h(

  v16i8_r = __msa_binsli_b(v16i8_r, v16i8_a, 3); // CHECK: call <16 x i8>  @llvm.mips.binsli.b(

  v8i16_r = __msa_binsli_h(v8i16_r, v8i16_a, 8); // CHECK: call <8  x i16> @llvm.mips.binsli.h(

  v4i32_r = __msa_binsli_w(v4i32_r, v4i32_a, 25); // CHECK: call <4  x i32> @llvm.mips.binsli.w(

  v2i64_r = __msa_binsli_d(v2i64_r, v2i64_a, 25); // CHECK: call <2  x i64> @llvm.mips.binsli.d(
@@ -158,8 +158,8 @@ void test(void) { 
  v4i32_r = __msa_binsr_w(v4i32_r, v4i32_a, v4i32_b); // CHECK: call <4  x i32> @llvm.mips.binsr.w(

  v2i64_r = __msa_binsr_d(v2i64_r, v2i64_a, v2i64_b); // CHECK: call <2  x i64> @llvm.mips.binsr.d(



  v16i8_r = __msa_binsri_b(v16i8_r, v16i8_a, 25); // CHECK: call <16 x i8>  @llvm.mips.binsri.b(

  v8i16_r = __msa_binsri_h(v8i16_r, v8i16_a, 25); // CHECK: call <8  x i16> @llvm.mips.binsri.h(

  v16i8_r = __msa_binsri_b(v16i8_r, v16i8_a, 5); // CHECK: call <16 x i8>  @llvm.mips.binsri.b(

  v8i16_r = __msa_binsri_h(v8i16_r, v8i16_a, 15); // CHECK: call <8  x i16> @llvm.mips.binsri.h(

  v4i32_r = __msa_binsri_w(v4i32_r, v4i32_a, 25); // CHECK: call <4  x i32> @llvm.mips.binsri.w(

  v2i64_r = __msa_binsri_d(v2i64_r, v2i64_a, 25); // CHECK: call <2  x i64> @llvm.mips.binsri.d(
@@ -182,8 +182,8 @@ void test(void) { 
  v4i32_r = __msa_bneg_w(v4i32_a, v4i32_b); // CHECK: call <4  x i32> @llvm.mips.bneg.w(

  v2i64_r = __msa_bneg_d(v2i64_a, v2i64_b); // CHECK: call <2  x i64> @llvm.mips.bneg.d(



  v16i8_r = __msa_bnegi_b(v16i8_a, 25); // CHECK: call <16 x i8>  @llvm.mips.bnegi.b(

  v8i16_r = __msa_bnegi_h(v8i16_a, 25); // CHECK: call <8  x i16> @llvm.mips.bnegi.h(

  v16i8_r = __msa_bnegi_b(v16i8_a, 6); // CHECK: call <16 x i8>  @llvm.mips.bnegi.b(

  v8i16_r = __msa_bnegi_h(v8i16_a, 14); // CHECK: call <8  x i16> @llvm.mips.bnegi.h(

  v4i32_r = __msa_bnegi_w(v4i32_a, 25); // CHECK: call <4  x i32> @llvm.mips.bnegi.w(

  v2i64_r = __msa_bnegi_d(v2i64_a, 25); // CHECK: call <2  x i64> @llvm.mips.bnegi.d(
@@ -206,8 +206,8 @@ void test(void) { 
  v4i32_r = __msa_bset_w(v4i32_a, v4i32_b); // CHECK: call <4  x i32> @llvm.mips.bset.w(

  v2i64_r = __msa_bset_d(v2i64_a, v2i64_b); // CHECK: call <2  x i64> @llvm.mips.bset.d(



  v16i8_r = __msa_bseti_b(v16i8_a, 25); // CHECK: call <16 x i8>  @llvm.mips.bseti.b(

  v8i16_r = __msa_bseti_h(v8i16_a, 25); // CHECK: call <8  x i16> @llvm.mips.bseti.h(

  v16i8_r = __msa_bseti_b(v16i8_a, 5); // CHECK: call <16 x i8>  @llvm.mips.bseti.b(

  v8i16_r = __msa_bseti_h(v8i16_a, 15); // CHECK: call <8  x i16> @llvm.mips.bseti.h(

  v4i32_r = __msa_bseti_w(v4i32_a, 25); // CHECK: call <4  x i32> @llvm.mips.bseti.w(

  v2i64_r = __msa_bseti_d(v2i64_a, 25); // CHECK: call <2  x i64> @llvm.mips.bseti.d(
@@ -223,10 +223,10 @@ void test(void) { 
  v4i32_r = __msa_ceq_w(v4i32_a, v4i32_b); // CHECK: call <4  x i32> @llvm.mips.ceq.w(

  v2i64_r = __msa_ceq_d(v2i64_a, v2i64_b); // CHECK: call <2  x i64> @llvm.mips.ceq.d(



  v16i8_r = __msa_ceqi_b(v16i8_a, 25); // CHECK: call <16 x i8>  @llvm.mips.ceqi.b(

  v8i16_r = __msa_ceqi_h(v8i16_a, 25); // CHECK: call <8  x i16> @llvm.mips.ceqi.h(

  v4i32_r = __msa_ceqi_w(v4i32_a, 25); // CHECK: call <4  x i32> @llvm.mips.ceqi.w(

  v2i64_r = __msa_ceqi_d(v2i64_a, 25); // CHECK: call <2  x i64> @llvm.mips.ceqi.d(

  v16i8_r = __msa_ceqi_b(v16i8_a, -3); // CHECK: call <16 x i8>  @llvm.mips.ceqi.b(

  v8i16_r = __msa_ceqi_h(v8i16_a, -12); // CHECK: call <8  x i16> @llvm.mips.ceqi.h(

  v4i32_r = __msa_ceqi_w(v4i32_a, 14); // CHECK: call <4  x i32> @llvm.mips.ceqi.w(

  v2i64_r = __msa_ceqi_d(v2i64_a, 15); // CHECK: call <2  x i64> @llvm.mips.ceqi.d(



  int_r = __msa_cfcmsa(1); // CHECK: call i32 @llvm.mips.cfcmsa(
@@ -240,10 +240,10 @@ void test(void) { 
  v4u32_r = __msa_cle_u_w(v4u32_a, v4u32_b); // CHECK: call <4  x i32> @llvm.mips.cle.u.w(

  v2u64_r = __msa_cle_u_d(v2u64_a, v2u64_b); // CHECK: call <2  x i64> @llvm.mips.cle.u.d(



  v16i8_r = __msa_clei_s_b(v16i8_a, 25); // CHECK: call <16 x i8>  @llvm.mips.clei.s.b(

  v8i16_r = __msa_clei_s_h(v8i16_a, 25); // CHECK: call <8  x i16> @llvm.mips.clei.s.h(

  v4i32_r = __msa_clei_s_w(v4i32_a, 25); // CHECK: call <4  x i32> @llvm.mips.clei.s.w(

  v2i64_r = __msa_clei_s_d(v2i64_a, 25); // CHECK: call <2  x i64> @llvm.mips.clei.s.d(

  v16i8_r = __msa_clei_s_b(v16i8_a, 12); // CHECK: call <16 x i8>  @llvm.mips.clei.s.b(

  v8i16_r = __msa_clei_s_h(v8i16_a, 13); // CHECK: call <8  x i16> @llvm.mips.clei.s.h(

  v4i32_r = __msa_clei_s_w(v4i32_a, 14); // CHECK: call <4  x i32> @llvm.mips.clei.s.w(

  v2i64_r = __msa_clei_s_d(v2i64_a, 15); // CHECK: call <2  x i64> @llvm.mips.clei.s.d(



  v16u8_r = __msa_clei_u_b(v16u8_a, 25); // CHECK: call <16 x i8>  @llvm.mips.clei.u.b(

  v8u16_r = __msa_clei_u_h(v8u16_a, 25); // CHECK: call <8  x i16> @llvm.mips.clei.u.h(
@@ -260,10 +260,10 @@ void test(void) { 
  v4u32_r = __msa_clt_u_w(v4u32_a, v4u32_b); // CHECK: call <4  x i32> @llvm.mips.clt.u.w(

  v2u64_r = __msa_clt_u_d(v2u64_a, v2u64_b); // CHECK: call <2  x i64> @llvm.mips.clt.u.d(



  v16i8_r = __msa_clti_s_b(v16i8_a, 25); // CHECK: call <16 x i8>  @llvm.mips.clti.s.b(

  v8i16_r = __msa_clti_s_h(v8i16_a, 25); // CHECK: call <8  x i16> @llvm.mips.clti.s.h(

  v4i32_r = __msa_clti_s_w(v4i32_a, 25); // CHECK: call <4  x i32> @llvm.mips.clti.s.w(

  v2i64_r = __msa_clti_s_d(v2i64_a, 25); // CHECK: call <2  x i64> @llvm.mips.clti.s.d(

  v16i8_r = __msa_clti_s_b(v16i8_a, 15); // CHECK: call <16 x i8>  @llvm.mips.clti.s.b(

  v8i16_r = __msa_clti_s_h(v8i16_a, 15); // CHECK: call <8  x i16> @llvm.mips.clti.s.h(

  v4i32_r = __msa_clti_s_w(v4i32_a, 15); // CHECK: call <4  x i32> @llvm.mips.clti.s.w(

  v2i64_r = __msa_clti_s_d(v2i64_a, 15); // CHECK: call <2  x i64> @llvm.mips.clti.s.d(



  v16u8_r = __msa_clti_u_b(v16u8_a, 25); // CHECK: call <16 x i8>  @llvm.mips.clti.u.b(

  v8u16_r = __msa_clti_u_h(v8u16_a, 25); // CHECK: call <8  x i16> @llvm.mips.clti.u.h(
@@ -387,11 +387,11 @@ void test(void) { 
  v4i32_r = __msa_fill_w(3); // CHECK: call <4  x i32> @llvm.mips.fill.w(

  v2i64_r = __msa_fill_d(3); // CHECK: call <2  x i64> @llvm.mips.fill.d(



  v4f32_r = __msa_flog2_w(v8f16_a); // CHECK: call <4 x float>  @llvm.mips.flog2.w(

  v2f64_r = __msa_flog2_d(v4f32_a); // CHECK: call <2 x double> @llvm.mips.flog2.d(

  v4f32_r = __msa_flog2_w(v4f32_a); // CHECK: call <4 x float>  @llvm.mips.flog2.w(

  v2f64_r = __msa_flog2_d(v2f64_a); // CHECK: call <2 x double> @llvm.mips.flog2.d(



  v4f32_r = __msa_fmadd_w(v8f16_r, v8f16_a, v8f16_b); // CHECK: call <4 x float>  @llvm.mips.fmadd.w(

  v2f64_r = __msa_fmadd_d(v4f32_r, v4f32_a, v4f32_b); // CHECK: call <2 x double> @llvm.mips.fmadd.d(

  v4f32_r = __msa_fmadd_w(v4f32_r, v4f32_a, v4f32_b); // CHECK: call <4 x float>  @llvm.mips.fmadd.w(

  v2f64_r = __msa_fmadd_d(v2f64_r, v2f64_a, v2f64_b); // CHECK: call <2 x double> @llvm.mips.fmadd.d(



  v4f32_r = __msa_fmax_w(v4f32_a, v4f32_b); // CHECK: call <4 x float>  @llvm.mips.fmax.w(

  v2f64_r = __msa_fmax_d(v2f64_a, v2f64_b); // CHECK: call <2 x double> @llvm.mips.fmax.d(
@@ -405,20 +405,20 @@ void test(void) { 
  v4f32_r = __msa_fmin_a_w(v4f32_a, v4f32_b); // CHECK: call <4 x float>  @llvm.mips.fmin.a.w(

  v2f64_r = __msa_fmin_a_d(v2f64_a, v2f64_b); // CHECK: call <2 x double> @llvm.mips.fmin.a.d(



  v4f32_r = __msa_fmsub_w(v8f16_r, v8f16_a, v8f16_b); // CHECK: call <4 x float>  @llvm.mips.fmsub.w(

  v2f64_r = __msa_fmsub_d(v4f32_r, v4f32_a, v4f32_b); // CHECK: call <2 x double> @llvm.mips.fmsub.d(

  v4f32_r = __msa_fmsub_w(v4f32_r, v4f32_a, v4f32_b); // CHECK: call <4 x float>  @llvm.mips.fmsub.w(

  v2f64_r = __msa_fmsub_d(v2f64_r, v2f64_a, v2f64_b); // CHECK: call <2 x double> @llvm.mips.fmsub.d(



  v4f32_r = __msa_fmul_w(v4f32_a, v4f32_b); // CHECK: call <4 x float>  @llvm.mips.fmul.w(

  v2f64_r = __msa_fmul_d(v2f64_a, v2f64_b); // CHECK: call <2 x double> @llvm.mips.fmul.d(



  v4f32_r = __msa_frint_w(v8f16_a); // CHECK: call <4 x float>  @llvm.mips.frint.w(

  v2f64_r = __msa_frint_d(v4f32_a); // CHECK: call <2 x double> @llvm.mips.frint.d(

  v4f32_r = __msa_frint_w(v4f32_a); // CHECK: call <4 x float>  @llvm.mips.frint.w(

  v2f64_r = __msa_frint_d(v2f64_a); // CHECK: call <2 x double> @llvm.mips.frint.d(



  v4f32_r = __msa_frcp_w(v8f16_a); // CHECK: call <4 x float>  @llvm.mips.frcp.w(

  v2f64_r = __msa_frcp_d(v4f32_a); // CHECK: call <2 x double> @llvm.mips.frcp.d(

  v4f32_r = __msa_frcp_w(v4f32_a); // CHECK: call <4 x float>  @llvm.mips.frcp.w(

  v2f64_r = __msa_frcp_d(v2f64_a); // CHECK: call <2 x double> @llvm.mips.frcp.d(



  v4f32_r = __msa_frsqrt_w(v8f16_a); // CHECK: call <4 x float>  @llvm.mips.frsqrt.w(

  v2f64_r = __msa_frsqrt_d(v4f32_a); // CHECK: call <2 x double> @llvm.mips.frsqrt.d(

  v4f32_r = __msa_frsqrt_w(v4f32_a); // CHECK: call <4 x float>  @llvm.mips.frsqrt.w(

  v2f64_r = __msa_frsqrt_d(v2f64_a); // CHECK: call <2 x double> @llvm.mips.frsqrt.d(



  v4i32_r = __msa_fseq_w(v4f32_a, v4f32_b); // CHECK: call <4 x i32> @llvm.mips.fseq.w(

  v2i64_r = __msa_fseq_d(v2f64_a, v2f64_b); // CHECK: call <2 x i64> @llvm.mips.fseq.d(
@@ -438,8 +438,8 @@ void test(void) { 
  v4i32_r = __msa_fsor_w(v4f32_a, v4f32_b); // CHECK: call <4 x i32> @llvm.mips.fsor.w(

  v2i64_r = __msa_fsor_d(v2f64_a, v2f64_b); // CHECK: call <2 x i64> @llvm.mips.fsor.d(



  v4f32_r = __msa_fsqrt_w(v8f16_a); // CHECK: call <4 x float>  @llvm.mips.fsqrt.w(

  v2f64_r = __msa_fsqrt_d(v4f32_a); // CHECK: call <2 x double> @llvm.mips.fsqrt.d(

  v4f32_r = __msa_fsqrt_w(v4f32_a); // CHECK: call <4 x float>  @llvm.mips.fsqrt.w(

  v2f64_r = __msa_fsqrt_d(v2f64_a); // CHECK: call <2 x double> @llvm.mips.fsqrt.d(



  v4f32_r = __msa_fsub_w(v4f32_a, v4f32_b); // CHECK: call <4 x float>  @llvm.mips.fsub.w(

  v2f64_r = __msa_fsub_d(v2f64_a, v2f64_b); // CHECK: call <2 x double> @llvm.mips.fsub.d(
@@ -520,10 +520,10 @@ void test(void) { 
  v4i32_r = __msa_insve_w(v4i32_r, 1, v4i32_a); // CHECK: call <4  x i32> @llvm.mips.insve.w(

  v2i64_r = __msa_insve_d(v2i64_r, 1, v2i64_a); // CHECK: call <2  x i64> @llvm.mips.insve.d(



  v16i8_r = __msa_ld_b(&v16i8_a, 1); // CHECK: call <16 x i8>  @llvm.mips.ld.b(

  v8i16_r = __msa_ld_h(&v8i16_a, 2); // CHECK: call <8  x i16> @llvm.mips.ld.h(

  v4i32_r = __msa_ld_w(&v4i32_a, 4); // CHECK: call <4  x i32> @llvm.mips.ld.w(

  v2i64_r = __msa_ld_d(&v2i64_a, 8); // CHECK: call <2  x i64> @llvm.mips.ld.d(

  v16i8_r = __msa_ld_b(&v16i8_a, 16); // CHECK: call <16 x i8>  @llvm.mips.ld.b(

  v8i16_r = __msa_ld_h(&v8i16_a, 32); // CHECK: call <8  x i16> @llvm.mips.ld.h(

  v4i32_r = __msa_ld_w(&v4i32_a, 48); // CHECK: call <4  x i32> @llvm.mips.ld.w(

  v2i64_r = __msa_ld_d(&v2i64_a, 96); // CHECK: call <2  x i64> @llvm.mips.ld.d(



  v16i8_r = __msa_ldi_b(3); // CHECK: call <16 x i8>  @llvm.mips.ldi.b(

  v8i16_r = __msa_ldi_h(3); // CHECK: call <8  x i16> @llvm.mips.ldi.h(
@@ -694,15 +694,15 @@ void test(void) { 
  v8i16_r = __msa_shf_h(v8i16_a, 3); // CHECK: call <8  x i16> @llvm.mips.shf.h(

  v4i32_r = __msa_shf_w(v4i32_a, 3); // CHECK: call <4  x i32> @llvm.mips.shf.w(



  v16i8_r = __msa_sld_b(v16i8_r, v16i8_a, 10); // CHECK: call <16 x i8>  @llvm.mips.sld.b(

  v8i16_r = __msa_sld_h(v8i16_r, v8i16_a, 10); // CHECK: call <8  x i16> @llvm.mips.sld.h(

  v4i32_r = __msa_sld_w(v4i32_r, v4i32_a, 10); // CHECK: call <4  x i32> @llvm.mips.sld.w(

  v2i64_r = __msa_sld_d(v2i64_r, v2i64_a, 10); // CHECK: call <2  x i64> @llvm.mips.sld.d(

  v16i8_r = __msa_sld_b(v16i8_r, v16i8_a, 7); // CHECK: call <16 x i8>  @llvm.mips.sld.b(

  v8i16_r = __msa_sld_h(v8i16_r, v8i16_a, 5); // CHECK: call <8  x i16> @llvm.mips.sld.h(

  v4i32_r = __msa_sld_w(v4i32_r, v4i32_a, 3); // CHECK: call <4  x i32> @llvm.mips.sld.w(

  v2i64_r = __msa_sld_d(v2i64_r, v2i64_a, 1); // CHECK: call <2  x i64> @llvm.mips.sld.d(



  v16i8_r = __msa_sldi_b(v16i8_r, v16i8_a, 3); // CHECK: call <16 x i8>  @llvm.mips.sldi.b(

  v16i8_r = __msa_sldi_b(v16i8_r, v16i8_a, 7); // CHECK: call <16 x i8>  @llvm.mips.sldi.b(

  v8i16_r = __msa_sldi_h(v8i16_r, v8i16_a, 3); // CHECK: call <8  x i16> @llvm.mips.sldi.h(

  v4i32_r = __msa_sldi_w(v4i32_r, v4i32_a, 3); // CHECK: call <4  x i32> @llvm.mips.sldi.w(

  v2i64_r = __msa_sldi_d(v2i64_r, v2i64_a, 3); // CHECK: call <2  x i64> @llvm.mips.sldi.d(

  v4i32_r = __msa_sldi_w(v4i32_r, v4i32_a, 2); // CHECK: call <4  x i32> @llvm.mips.sldi.w(

  v2i64_r = __msa_sldi_d(v2i64_r, v2i64_a, 1); // CHECK: call <2  x i64> @llvm.mips.sldi.d(



  v16i8_r = __msa_sll_b(v16i8_a, v16i8_b); // CHECK: call <16 x i8>  @llvm.mips.sll.b(

  v8i16_r = __msa_sll_h(v8i16_a, v8i16_b); // CHECK: call <8  x i16> @llvm.mips.sll.h(
@@ -722,7 +722,7 @@ void test(void) { 
  v16i8_r = __msa_splati_b(v16i8_a, 3); // CHECK: call <16 x i8>  @llvm.mips.splati.b(

  v8i16_r = __msa_splati_h(v8i16_a, 3); // CHECK: call <8  x i16> @llvm.mips.splati.h(

  v4i32_r = __msa_splati_w(v4i32_a, 3); // CHECK: call <4  x i32> @llvm.mips.splati.w(

  v2i64_r = __msa_splati_d(v2i64_a, 3); // CHECK: call <2  x i64> @llvm.mips.splati.d(

  v2i64_r = __msa_splati_d(v2i64_a, 1); // CHECK: call <2  x i64> @llvm.mips.splati.d(



  v16i8_r = __msa_sra_b(v16i8_a, v16i8_b); // CHECK: call <16 x i8>  @llvm.mips.sra.b(

  v8i16_r = __msa_sra_h(v8i16_a, v8i16_b); // CHECK: call <8  x i16> @llvm.mips.sra.h(
@@ -764,10 +764,10 @@ void test(void) { 
  v4i32_r = __msa_srlri_w(v4i32_a, 3); // CHECK: call <4  x i32> @llvm.mips.srlri.w(

  v2i64_r = __msa_srlri_d(v2i64_a, 3); // CHECK: call <2  x i64> @llvm.mips.srlri.d(



  __msa_st_b(v16i8_b, &v16i8_a, 1); // CHECK: call void @llvm.mips.st.b(

  __msa_st_h(v8i16_b, &v8i16_a, 2); // CHECK: call void @llvm.mips.st.h(

  __msa_st_w(v4i32_b, &v4i32_a, 4); // CHECK: call void @llvm.mips.st.w(

  __msa_st_d(v2i64_b, &v2i64_a, 8); // CHECK: call void @llvm.mips.st.d(

  __msa_st_b(v16i8_b, &v16i8_a, 16); // CHECK: call void @llvm.mips.st.b(

  __msa_st_h(v8i16_b, &v8i16_a, 32); // CHECK: call void @llvm.mips.st.h(

  __msa_st_w(v4i32_b, &v4i32_a, 48); // CHECK: call void @llvm.mips.st.w(

  __msa_st_d(v2i64_b, &v2i64_a, 96); // CHECK: call void @llvm.mips.st.d(



  v16i8_r = __msa_subs_s_b(v16i8_a, v16i8_b); // CHECK: call <16 x i8>  @llvm.mips.subs.s.b(

  v8i16_r = __msa_subs_s_h(v8i16_a, v8i16_b); // CHECK: call <8  x i16> @llvm.mips.subs.s.h(