Commit a21becce authored by Craig Topper's avatar Craig Topper
Browse files

[X86] Add STRICT versions of CVTTP2SI, CVTTP2UI, CMPM, and CMPP. 

Differential Revision: https://reviews.llvm.org/D71850
parent 3cb934c9

llvm/lib/Target/X86/X86ISelDAGToDAG.cpp

+12 −11
Original line number Diff line number Diff line
@@ -537,15 +537,16 @@ namespace { 
// type.

static bool isLegalMaskCompare(SDNode *N, const X86Subtarget *Subtarget) {

  unsigned Opcode = N->getOpcode();

  if (Opcode == X86ISD::CMPM || Opcode == ISD::SETCC ||

      Opcode == X86ISD::CMPM_SAE || Opcode == X86ISD::VFPCLASS) {

  if (Opcode == X86ISD::CMPM || Opcode == X86ISD::STRICT_CMPM ||

      Opcode == ISD::SETCC || Opcode == X86ISD::CMPM_SAE ||

      Opcode == X86ISD::VFPCLASS) {

    // We can get 256-bit 8 element types here without VLX being enabled. When

    // this happens we will use 512-bit operations and the mask will not be

    // zero extended.

    EVT OpVT = N->getOperand(0).getValueType();

    // The first operand of X86ISD::CMPM is chain, so we need to get the second

    // operand.

    if (Opcode == X86ISD::CMPM)

    // The first operand of X86ISD::STRICT_CMPM is chain, so we need to get the

    // second operand.

    if (Opcode == X86ISD::STRICT_CMPM)

      OpVT = N->getOperand(1).getValueType();

    if (OpVT.is256BitVector() || OpVT.is128BitVector())

      return Subtarget->hasVLX();
@@ -827,9 +828,9 @@ void X86DAGToDAGISel::PreprocessISelDAG() { 
      unsigned NewOpc;

      switch (N->getOpcode()) {

      default: llvm_unreachable("Unexpected opcode!");

      case ISD::STRICT_FP_TO_SINT:

      case ISD::STRICT_FP_TO_SINT: NewOpc = X86ISD::STRICT_CVTTP2SI; break;

      case ISD::FP_TO_SINT:        NewOpc = X86ISD::CVTTP2SI;        break;

      case ISD::STRICT_FP_TO_UINT:

      case ISD::STRICT_FP_TO_UINT: NewOpc = X86ISD::STRICT_CVTTP2UI; break;

      case ISD::FP_TO_UINT:        NewOpc = X86ISD::CVTTP2UI;        break;

      }

      SDValue Res;
@@ -839,8 +840,8 @@ void X86DAGToDAGISel::PreprocessISelDAG() { 
                            {N->getOperand(0), N->getOperand(1)});

      else

        Res =

            CurDAG->getNode(NewOpc, SDLoc(N), {N->getValueType(0), MVT::Other},

                            {CurDAG->getEntryNode(), N->getOperand(0)});

            CurDAG->getNode(NewOpc, SDLoc(N), N->getValueType(0),

                            N->getOperand(0));

      --I;

      if (N->isStrictFPOpcode()) {

        SDValue From[] = {SDValue(N, 0), SDValue(N, 1)};

llvm/lib/Target/X86/X86ISelLowering.cpp

+79 −83
Original line number Diff line number Diff line
@@ -19782,14 +19782,16 @@ SDValue X86TargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const { 
        return Res;

      }

      SDValue Res, Chain;

      unsigned Opc = IsSigned ? X86ISD::CVTTP2SI : X86ISD::CVTTP2UI;

      if (IsStrict) {

        unsigned Opc = IsSigned ? X86ISD::STRICT_CVTTP2SI

                                : X86ISD::STRICT_CVTTP2UI;

        Res =

            DAG.getNode(Opc, dl, {ResVT, MVT::Other}, {Op->getOperand(0), Src});

        Chain = Res.getValue(1);

      } else

        Res = DAG.getNode(Opc, dl, {ResVT, MVT::Other},

                          {DAG.getEntryNode(), Src});

      } else {

        unsigned Opc = IsSigned ? X86ISD::CVTTP2SI : X86ISD::CVTTP2UI;

        Res = DAG.getNode(Opc, dl, ResVT, Src);

      }

      Res = DAG.getNode(ISD::TRUNCATE, dl, TruncVT, Res);

      Res = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i1, Res,

                        DAG.getIntPtrConstant(0, dl));
@@ -19802,14 +19804,13 @@ SDValue X86TargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const { 
    if (VT == MVT::v2i64 && SrcVT  == MVT::v2f32) {

      SDValue Tmp = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32, Src,

                                DAG.getUNDEF(MVT::v2f32));

      unsigned Opc = IsSigned ? X86ISD::CVTTP2SI : X86ISD::CVTTP2UI;

      SDValue Res, Chain;

      if (IsStrict) {

        Res = DAG.getNode(Opc, dl, {VT, MVT::Other}, {Op->getOperand(0), Tmp});

        Chain = Res.getValue(1);

        return DAG.getMergeValues({Res, Chain}, dl);

        unsigned Opc = IsSigned ? X86ISD::STRICT_CVTTP2SI

                                : X86ISD::STRICT_CVTTP2UI;

        return DAG.getNode(Opc, dl, {VT, MVT::Other}, {Op->getOperand(0), Tmp});

      }

      return DAG.getNode(Opc, dl, {VT, MVT::Other}, {DAG.getEntryNode(), Tmp});

      unsigned Opc = IsSigned ? X86ISD::CVTTP2SI : X86ISD::CVTTP2UI;

      return DAG.getNode(Opc, dl, VT, Tmp);

    }















    return SDValue();










@@ -20972,8 +20973,6 @@ static SDValue LowerVSETCC(SDValue Op, const X86Subtarget &Subtarget,













                           SelectionDAG &DAG) {















  bool IsStrict = Op.getOpcode() == ISD::STRICT_FSETCC ||















                  Op.getOpcode() == ISD::STRICT_FSETCCS;













  bool IsSignaling = Op.getOpcode() == ISD::STRICT_FSETCCS;













  SDValue Chain = IsStrict ? Op.getOperand(0) : DAG.getEntryNode();















  SDValue Op0 = Op.getOperand(IsStrict ? 1 : 0);















  SDValue Op1 = Op.getOperand(IsStrict ? 2 : 1);















  SDValue CC = Op.getOperand(IsStrict ? 3 : 2);









@@ -20988,12 +20987,15 @@ static SDValue LowerVSETCC(SDValue Op, const X86Subtarget &Subtarget,













    assert(EltVT == MVT::f32 || EltVT == MVT::f64);















#endif



























    bool IsSignaling = Op.getOpcode() == ISD::STRICT_FSETCCS;













    SDValue Chain = IsStrict ? Op.getOperand(0) : SDValue();



























    unsigned Opc;















    if (Subtarget.hasAVX512() && VT.getVectorElementType() == MVT::i1) {















      assert(VT.getVectorNumElements() <= 16);













      Opc = X86ISD::CMPM;













      Opc = IsStrict ? X86ISD::STRICT_CMPM : X86ISD::CMPM;















    } else {













      Opc = X86ISD::CMPP;













      Opc = IsStrict ? X86ISD::STRICT_CMPP : X86ISD::CMPP;















      // The SSE/AVX packed FP comparison nodes are defined with a















      // floating-point vector result that matches the operand type. This allows















      // them to work with an SSE1 target (integer vector types are not legal).










@@ -21044,36 +21046,50 @@ static SDValue LowerVSETCC(SDValue Op, const X86Subtarget &Subtarget,













          CombineOpc = X86ISD::FAND;















        }



























        SDValue Cmp0 = DAG.getNode(













        SDValue Cmp0, Cmp1;













        if (IsStrict) {













          Cmp0 = DAG.getNode(















              Opc, dl, {VT, MVT::Other},















              {Chain, Op0, Op1, DAG.getTargetConstant(CC0, dl, MVT::i8)});













        SDValue Cmp1 = DAG.getNode(













          Cmp1 = DAG.getNode(















              Opc, dl, {VT, MVT::Other},















              {Chain, Op0, Op1, DAG.getTargetConstant(CC1, dl, MVT::i8)});















          Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Cmp0.getValue(1),















                              Cmp1.getValue(1));













        } else {













          Cmp0 = DAG.getNode(













              Opc, dl, VT, Op0, Op1, DAG.getTargetConstant(CC0, dl, MVT::i8));













          Cmp1 = DAG.getNode(













              Opc, dl, VT, Op0, Op1, DAG.getTargetConstant(CC1, dl, MVT::i8));













        }















        Cmp = DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);















      } else {













        if (IsStrict) {















          Cmp = DAG.getNode(















              Opc, dl, {VT, MVT::Other},















              {Chain, Op0, Op1, DAG.getTargetConstant(SSECC, dl, MVT::i8)});















          Chain = Cmp.getValue(1);













        } else













          Cmp = DAG.getNode(













              Opc, dl, VT, Op0, Op1, DAG.getTargetConstant(SSECC, dl, MVT::i8));















      }















    } else {















      // Handle all other FP comparisons here.













      if (IsStrict)













      if (IsStrict) {















        // Make a flip on already signaling CCs before setting bit 4 of AVX CC.















        SSECC |= (IsAlwaysSignaling ^ IsSignaling) << 4;















        Cmp = DAG.getNode(















            Opc, dl, {VT, MVT::Other},















            {Chain, Op0, Op1, DAG.getTargetConstant(SSECC, dl, MVT::i8)});















        Chain = Cmp.getValue(1);













      } else













        Cmp = DAG.getNode(













            Opc, dl, VT, Op0, Op1, DAG.getTargetConstant(SSECC, dl, MVT::i8));















    }





























    // If this is SSE/AVX CMPP, bitcast the result back to integer to match the















    // result type of SETCC. The bitcast is expected to be optimized away















    // during combining/isel.













    if (Opc == X86ISD::CMPP)















    Cmp = DAG.getBitcast(Op.getSimpleValueType(), Cmp);





























    if (IsStrict)










@@ -23151,26 +23167,6 @@ static SDValue recoverFramePointer(SelectionDAG &DAG, const Function *Fn,













  return DAG.getNode(ISD::SUB, dl, PtrVT, RegNodeBase, ParentFrameOffset);















}



























// We share some nodes between STRICT and non STRICT FP intrinsics.













// For these nodes, we need chain them to entry token if they are not called













// by STRICT FP intrinsics.













static SDValue getProperNode(unsigned Opcode, const SDLoc &dl, EVT VT,













                             ArrayRef<SDValue> Ops, SelectionDAG &DAG) {













  switch (Opcode) {













  default:













    return DAG.getNode(Opcode, dl, VT, Ops);













  case X86ISD::CVTTP2SI:













  case X86ISD::CVTTP2UI:













  case X86ISD::CMPP:













  case X86ISD::CMPM:













    break;













  }

























  SmallVector<SDValue, 6> NewOps = {DAG.getEntryNode()};













  NewOps.append(Ops.begin(), Ops.end());













  return DAG.getNode(Opcode, dl, {VT, MVT::Other}, NewOps);













}



























SDValue X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,















                                                   SelectionDAG &DAG) const {















  // Helper to detect if the operand is CUR_DIRECTION rounding mode.










@@ -23232,8 +23228,8 @@ SDValue X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,













        if (!isRoundModeCurDirection(Rnd))















          return SDValue();















      }













      return getProperNode(IntrData->Opc0, dl, Op.getValueType(),













                           Op.getOperand(1), DAG);













      return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(),













                         Op.getOperand(1));















    }















    case INTR_TYPE_1OP_SAE: {















      SDValue Sae = Op.getOperand(2);










@@ -23304,8 +23300,8 @@ SDValue X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,













          return SDValue();















      }



























      return getProperNode(IntrData->Opc0, dl, Op.getValueType(),













                           {Src1, Src2, Src3}, DAG);













      return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(),













                         {Src1, Src2, Src3});















    }















    case INTR_TYPE_4OP:















      return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),









@@ -23330,7 +23326,7 @@ SDValue X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,













          return SDValue();















      }















      return getVectorMaskingNode(













          getProperNode(IntrData->Opc0, dl, VT, Src, DAG), Mask, PassThru,













          DAG.getNode(IntrData->Opc0, dl, VT, Src), Mask, PassThru,















          Subtarget, DAG);















    }















    case INTR_TYPE_1OP_MASK_SAE: {









@@ -23347,8 +23343,8 @@ SDValue X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,













      else















        return SDValue();



























      return getVectorMaskingNode(getProperNode(Opc, dl, VT, Src, DAG), Mask,













                                  PassThru, Subtarget, DAG);













      return getVectorMaskingNode(DAG.getNode(Opc, dl, VT, Src), Mask, PassThru,













                                  Subtarget, DAG);















    }















    case INTR_TYPE_SCALAR_MASK: {















      SDValue Src1 = Op.getOperand(1);










@@ -23554,8 +23550,8 @@ SDValue X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,













          return SDValue();















      }















      //default rounding mode













      return getProperNode(IntrData->Opc0, dl, MaskVT,













                           {Op.getOperand(1), Op.getOperand(2), CC}, DAG);













      return DAG.getNode(IntrData->Opc0, dl, MaskVT,













                         {Op.getOperand(1), Op.getOperand(2), CC});















    }















    case CMP_MASK_SCALAR_CC: {















      SDValue Src1 = Op.getOperand(1);










@@ -23750,13 +23746,13 @@ SDValue X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,













      SDValue Mask = Op.getOperand(3);





























      if (isAllOnesConstant(Mask))













        return getProperNode(IntrData->Opc0, dl, Op.getValueType(), Src, DAG);













        return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Src);





























      MVT SrcVT = Src.getSimpleValueType();















      MVT MaskVT = MVT::getVectorVT(MVT::i1, SrcVT.getVectorNumElements());















      Mask = getMaskNode(Mask, MaskVT, Subtarget, DAG, dl);













      return getProperNode(IntrData->Opc1, dl, Op.getValueType(),













                           {Src, PassThru, Mask}, DAG);













      return DAG.getNode(IntrData->Opc1, dl, Op.getValueType(),













                         {Src, PassThru, Mask});















    }















    case CVTPS2PH_MASK: {















      SDValue Src = Op.getOperand(1);










@@ -28666,16 +28662,18 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,













          // legalization to v8i32<-v8f64.















          return;















        }













        unsigned Opc = IsSigned ? X86ISD::CVTTP2SI : X86ISD::CVTTP2UI;















        SDValue Res;















        SDValue Chain;















        if (IsStrict) {













          unsigned Opc = IsSigned ? X86ISD::STRICT_CVTTP2SI













                                  : X86ISD::STRICT_CVTTP2UI;















          Res = DAG.getNode(Opc, dl, {MVT::v4i32, MVT::Other},















                            {N->getOperand(0), Src});















          Chain = Res.getValue(1);













        } else













          Res = DAG.getNode(Opc, dl, {MVT::v4i32, MVT::Other},













                            {DAG.getEntryNode(), Src});













        } else {













          unsigned Opc = IsSigned ? X86ISD::CVTTP2SI : X86ISD::CVTTP2UI;













          Res = DAG.getNode(Opc, dl, MVT::v4i32, Src);













        }















        Results.push_back(Res);















        if (IsStrict)















          Results.push_back(Chain);










@@ -29114,6 +29112,7 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {













  case X86ISD::COMI:               return "X86ISD::COMI";















  case X86ISD::UCOMI:              return "X86ISD::UCOMI";















  case X86ISD::CMPM:               return "X86ISD::CMPM";













  case X86ISD::STRICT_CMPM:        return "X86ISD::STRICT_CMPM";















  case X86ISD::CMPM_SAE:           return "X86ISD::CMPM_SAE";















  case X86ISD::SETCC:              return "X86ISD::SETCC";















  case X86ISD::SETCC_CARRY:        return "X86ISD::SETCC_CARRY";










@@ -29221,6 +29220,7 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {













  case X86ISD::VROTRI:             return "X86ISD::VROTRI";















  case X86ISD::VPPERM:             return "X86ISD::VPPERM";















  case X86ISD::CMPP:               return "X86ISD::CMPP";













  case X86ISD::STRICT_CMPP:        return "X86ISD::STRICT_CMPP";















  case X86ISD::PCMPEQ:             return "X86ISD::PCMPEQ";















  case X86ISD::PCMPGT:             return "X86ISD::PCMPGT";















  case X86ISD::PHMINPOS:           return "X86ISD::PHMINPOS";










@@ -29382,6 +29382,8 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {













  case X86ISD::UINT_TO_FP_RND:     return "X86ISD::UINT_TO_FP_RND";















  case X86ISD::CVTTP2SI:           return "X86ISD::CVTTP2SI";















  case X86ISD::CVTTP2UI:           return "X86ISD::CVTTP2UI";













  case X86ISD::STRICT_CVTTP2SI:    return "X86ISD::STRICT_CVTTP2SI";













  case X86ISD::STRICT_CVTTP2UI:    return "X86ISD::STRICT_CVTTP2UI";















  case X86ISD::MCVTTP2SI:          return "X86ISD::MCVTTP2SI";















  case X86ISD::MCVTTP2UI:          return "X86ISD::MCVTTP2UI";















  case X86ISD::CVTTP2SI_SAE:       return "X86ISD::CVTTP2SI_SAE";










@@ -34783,6 +34785,7 @@ static SDValue combineShuffle(SDNode *N, SelectionDAG &DAG,













      break;















    case X86ISD::CVTP2SI:   case X86ISD::CVTP2UI:















    case X86ISD::MCVTP2SI:  case X86ISD::MCVTP2UI:













    case X86ISD::CVTTP2SI:  case X86ISD::CVTTP2UI:















    case X86ISD::MCVTTP2SI: case X86ISD::MCVTTP2UI:















    case X86ISD::CVTSI2P:   case X86ISD::CVTUI2P:















    case X86ISD::MCVTSI2P:  case X86ISD::MCVTUI2P:









@@ -34791,8 +34794,8 @@ static SDValue combineShuffle(SDNode *N, SelectionDAG &DAG,













          In.getOperand(0).getValueType() == MVT::v2i64)















        return N->getOperand(0); // return the bitcast















      break;













    case X86ISD::CVTTP2SI:













    case X86ISD::CVTTP2UI:













    case X86ISD::STRICT_CVTTP2SI:













    case X86ISD::STRICT_CVTTP2UI:















      if (In.getOperand(1).getValueType() == MVT::v2f64 ||















          In.getOperand(1).getValueType() == MVT::v2i64)















        return N->getOperand(0);










@@ -42497,14 +42500,11 @@ static SDValue combineX86INT_TO_FP(SDNode *N, SelectionDAG &DAG,



























static SDValue combineCVTP2I_CVTTP2I(SDNode *N, SelectionDAG &DAG,















                                     TargetLowering::DAGCombinerInfo &DCI) {













  // FIXME: Handle strict fp nodes.















  EVT VT = N->getValueType(0);





























  // Convert a full vector load into vzload when not all bits are needed.













  SDValue In;













  if (N->getOpcode() == X86ISD::CVTTP2SI || N->getOpcode() == X86ISD::CVTTP2UI)













    In = N->getOperand(1);













  else













    In = N->getOperand(0);













  SDValue In = N->getOperand(0);















  MVT InVT = In.getSimpleValueType();















  if (VT.getVectorNumElements() < InVT.getVectorNumElements() &&















      ISD::isNormalLoad(In.getNode()) && In.hasOneUse()) {









@@ -42523,12 +42523,8 @@ static SDValue combineCVTP2I_CVTTP2I(SDNode *N, SelectionDAG &DAG,













                                  LN->getPointerInfo(),















                                  LN->getAlignment(),















                                  LN->getMemOperand()->getFlags());













      SDValue Convert = getProperNode(N->getOpcode(), dl, VT,













                                      DAG.getBitcast(InVT, VZLoad), DAG);













      if (Convert->getOpcode() == X86ISD::CVTTP2SI ||













          Convert->getOpcode() == X86ISD::CVTTP2UI)













        DCI.CombineTo(N, Convert.getValue(0), Convert.getValue(1));













      else













      SDValue Convert = DAG.getNode(N->getOpcode(), dl, VT,













                                    DAG.getBitcast(InVT, VZLoad));















      DCI.CombineTo(N, Convert);















      DAG.ReplaceAllUsesOfValueWith(SDValue(LN, 1), VZLoad.getValue(1));















      return SDValue(N, 0);

























llvm/lib/Target/X86/X86ISelLowering.h



+3
−0






























Original line number
Diff line number
Diff line








@@ -325,6 +325,7 @@ namespace llvm {





























      // Vector packed double/float comparison.















      CMPP,













      STRICT_CMPP,































      // Vector integer comparisons.















      PCMPEQ, PCMPGT,









@@ -337,6 +338,7 @@ namespace llvm {













      /// Vector comparison generating mask bits for fp and















      /// integer signed and unsigned data types.















      CMPM,













      STRICT_CMPM,















      // Vector comparison with SAE for FP values















      CMPM_SAE,


























@@ -504,6 +506,7 @@ namespace llvm {





























      // Vector float/double to signed/unsigned integer with truncation.















      CVTTP2SI, CVTTP2UI, CVTTP2SI_SAE, CVTTP2UI_SAE,













      STRICT_CVTTP2SI, STRICT_CVTTP2UI,















      // Scalar float/double to signed/unsigned integer with truncation.















      CVTTS2SI, CVTTS2UI, CVTTS2SI_SAE, CVTTS2UI_SAE,

















































llvm/lib/Target/X86/X86InstrAVX512.td



+41
−41




























File changed.
Preview size limit exceeded, changes collapsed.
























llvm/lib/Target/X86/X86InstrFragmentsSIMD.td



+21
−4






























Original line number
Diff line number
Diff line








@@ -169,10 +169,15 @@ def X86vshiftimm : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,





























def X86vshldq  : SDNode<"X86ISD::VSHLDQ",    X86vshiftimm>;















def X86vshrdq  : SDNode<"X86ISD::VSRLDQ",    X86vshiftimm>;













def X86cmpp    : SDNode<"X86ISD::CMPP",      SDTX86VFCMP, [SDNPHasChain]>;















def X86pcmpeq  : SDNode<"X86ISD::PCMPEQ", SDTIntBinOp, [SDNPCommutative]>;















def X86pcmpgt  : SDNode<"X86ISD::PCMPGT", SDTIntBinOp>;





























def X86cmpp    : SDNode<"X86ISD::CMPP",      SDTX86VFCMP>;













def X86strict_cmpp : SDNode<"X86ISD::STRICT_CMPP", SDTX86VFCMP, [SDNPHasChain]>;













def X86any_cmpp    : PatFrags<(ops node:$src1, node:$src2, node:$src3),













                               [(X86strict_cmpp node:$src1, node:$src2, node:$src3),













                                (X86cmpp node:$src1, node:$src2, node:$src3)]>;





























def X86CmpMaskCC :















      SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCVecEltisVT<0, i1>,















                       SDTCisVec<1>, SDTCisSameAs<2, 1>,









@@ -181,7 +186,11 @@ def X86CmpMaskCCScalar :













      SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisFP<1>, SDTCisSameAs<1, 2>,















                           SDTCisVT<3, i8>]>;





























def X86cmpm     : SDNode<"X86ISD::CMPM",     X86CmpMaskCC, [SDNPHasChain]>;













def X86cmpm     : SDNode<"X86ISD::CMPM",     X86CmpMaskCC>;













def X86strict_cmpm : SDNode<"X86ISD::STRICT_CMPM", X86CmpMaskCC, [SDNPHasChain]>;













def X86any_cmpm    : PatFrags<(ops node:$src1, node:$src2, node:$src3),













                               [(X86strict_cmpm node:$src1, node:$src2, node:$src3),













                                (X86cmpm node:$src1, node:$src2, node:$src3)]>;















def X86cmpmSAE  : SDNode<"X86ISD::CMPM_SAE", X86CmpMaskCC>;















def X86cmpms    : SDNode<"X86ISD::FSETCCM",   X86CmpMaskCCScalar>;















def X86cmpmsSAE : SDNode<"X86ISD::FSETCCM_SAE",   X86CmpMaskCCScalar>;










@@ -623,8 +632,16 @@ def X86cvtp2UIntRnd     : SDNode<"X86ISD::CVTP2UI_RND",  SDTFloatToIntRnd>;













// Vector without rounding mode































// cvtt fp-to-int staff













def X86cvttp2si      : SDNode<"X86ISD::CVTTP2SI",  SDTFloatToInt, [SDNPHasChain]>;













def X86cvttp2ui      : SDNode<"X86ISD::CVTTP2UI",  SDTFloatToInt, [SDNPHasChain]>;













def X86cvttp2si      : SDNode<"X86ISD::CVTTP2SI",  SDTFloatToInt>;













def X86cvttp2ui      : SDNode<"X86ISD::CVTTP2UI",  SDTFloatToInt>;













def X86strict_cvttp2si : SDNode<"X86ISD::STRICT_CVTTP2SI",  SDTFloatToInt, [SDNPHasChain]>;













def X86strict_cvttp2ui : SDNode<"X86ISD::STRICT_CVTTP2UI",  SDTFloatToInt, [SDNPHasChain]>;













def X86any_cvttp2si : PatFrags<(ops node:$src),













                               [(X86strict_cvttp2si node:$src),













                                (X86cvttp2si node:$src)]>;













def X86any_cvttp2ui : PatFrags<(ops node:$src),













                               [(X86strict_cvttp2ui node:$src),













                                (X86cvttp2ui node:$src)]>;































def X86VSintToFP      : SDNode<"X86ISD::CVTSI2P",  SDTVintToFP>;















def X86VUintToFP      : SDNode<"X86ISD::CVTUI2P",  SDTVintToFP>;