Commit a1b7db3e authored by Craig Topper's avatar Craig Topper
Browse files

[RISCV] Split __builtin_riscv_xperm4/8 into separate _32 and _64 builtins.

Part of an effort to remove uses of 'long' to mean XLen from the builtin
interfaces.

Also makes the builtin names match https://github.com/riscv-non-isa/riscv-c-api-doc/pull/44.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D154681
parent a4f553fc
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+4 −2
Original line number Diff line number Diff line
@@ -29,8 +29,10 @@ TARGET_BUILTIN(__builtin_riscv_clmulh, "LiLiLi", "nc", "zbc|zbkc")
TARGET_BUILTIN(__builtin_riscv_clmulr, "LiLiLi", "nc", "zbc")

// Zbkx
TARGET_BUILTIN(__builtin_riscv_xperm4, "LiLiLi", "nc", "zbkx")
TARGET_BUILTIN(__builtin_riscv_xperm8, "LiLiLi", "nc", "zbkx")
TARGET_BUILTIN(__builtin_riscv_xperm4_32, "iii", "nc", "zbkx,32bit")
TARGET_BUILTIN(__builtin_riscv_xperm4_64, "WiWiWi", "nc", "zbkx,64bit")
TARGET_BUILTIN(__builtin_riscv_xperm8_32, "iii", "nc", "zbkx,32bit")
TARGET_BUILTIN(__builtin_riscv_xperm8_64, "WiWiWi", "nc", "zbkx,64bit")

// Zbkb extension
TARGET_BUILTIN(__builtin_riscv_brev8, "LiLi", "nc", "zbkb")
+8 −4
Original line number Diff line number Diff line
@@ -20202,8 +20202,10 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID,
  case RISCV::BI__builtin_riscv_clmul:
  case RISCV::BI__builtin_riscv_clmulh:
  case RISCV::BI__builtin_riscv_clmulr:
  case RISCV::BI__builtin_riscv_xperm4:
  case RISCV::BI__builtin_riscv_xperm8:
  case RISCV::BI__builtin_riscv_xperm4_32:
  case RISCV::BI__builtin_riscv_xperm4_64:
  case RISCV::BI__builtin_riscv_xperm8_32:
  case RISCV::BI__builtin_riscv_xperm8_64:
  case RISCV::BI__builtin_riscv_brev8:
  case RISCV::BI__builtin_riscv_zip_32:
  case RISCV::BI__builtin_riscv_unzip_32: {
@@ -20245,10 +20247,12 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID,
      break;
    // Zbkx
    case RISCV::BI__builtin_riscv_xperm8:
    case RISCV::BI__builtin_riscv_xperm8_32:
    case RISCV::BI__builtin_riscv_xperm8_64:
      ID = Intrinsic::riscv_xperm8;
      break;
    case RISCV::BI__builtin_riscv_xperm4:
    case RISCV::BI__builtin_riscv_xperm4_32:
    case RISCV::BI__builtin_riscv_xperm4_64:
      ID = Intrinsic::riscv_xperm4;
      break;
+4 −4
Original line number Diff line number Diff line
@@ -13,9 +13,9 @@
// RV32ZBKX-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.xperm8.i32(i32 [[TMP0]], i32 [[TMP1]])
// RV32ZBKX-NEXT:    ret i32 [[TMP2]]
//
long xperm8(long rs1, long rs2)
int xperm8(int rs1, int rs2)
{
  return __builtin_riscv_xperm8(rs1, rs2);
  return __builtin_riscv_xperm8_32(rs1, rs2);
}

// RV32ZBKX-LABEL: @xperm4(
@@ -29,7 +29,7 @@ long xperm8(long rs1, long rs2)
// RV32ZBKX-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.xperm4.i32(i32 [[TMP0]], i32 [[TMP1]])
// RV32ZBKX-NEXT:    ret i32 [[TMP2]]
//
long xperm4(long rs1, long rs2)
int xperm4(int rs1, int rs2)
{
  return __builtin_riscv_xperm4(rs1, rs2);
  return __builtin_riscv_xperm4_32(rs1, rs2);
}
+2 −2
Original line number Diff line number Diff line
@@ -15,7 +15,7 @@
//
long xperm8(long rs1, long rs2)
{
  return __builtin_riscv_xperm8(rs1, rs2);
  return __builtin_riscv_xperm8_64(rs1, rs2);
}

// RV64ZBKX-LABEL: @xperm4(
@@ -31,5 +31,5 @@ long xperm8(long rs1, long rs2)
//
long xperm4(long rs1, long rs2)
{
  return __builtin_riscv_xperm4(rs1, rs2);
  return __builtin_riscv_xperm4_64(rs1, rs2);
}