Loading llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp +0 −12 Original line number Diff line number Diff line Loading @@ -1347,18 +1347,6 @@ void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI, } StringRef SIRegisterInfo::getRegAsmName(unsigned Reg) const { // FIXME: Rename flat_scr so we don't need to special case this. switch (Reg) { case AMDGPU::FLAT_SCR: return "flat_scratch"; case AMDGPU::FLAT_SCR_LO: return "flat_scratch_lo"; case AMDGPU::FLAT_SCR_HI: return "flat_scratch_hi"; default: break; } const TargetRegisterClass *RC = getMinimalPhysRegClass(Reg); unsigned Size = getRegSizeInBits(*RC); unsigned AltName = AMDGPU::NoRegAltName; Loading llvm/lib/Target/AMDGPU/SIRegisterInfo.td +1 −1 Original line number Diff line number Diff line Loading @@ -171,7 +171,7 @@ foreach Index = 0-15 in { multiclass FLAT_SCR_LOHI_m <string n, bits<16> ci_e, bits<16> vi_e> { def _ci : SIReg<n, ci_e>; def _vi : SIReg<n, vi_e>; def "" : SIReg<"", 0>; def "" : SIReg<n, 0>; } class FlatReg <Register lo, Register hi, bits<16> encoding> : Loading Loading
llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp +0 −12 Original line number Diff line number Diff line Loading @@ -1347,18 +1347,6 @@ void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI, } StringRef SIRegisterInfo::getRegAsmName(unsigned Reg) const { // FIXME: Rename flat_scr so we don't need to special case this. switch (Reg) { case AMDGPU::FLAT_SCR: return "flat_scratch"; case AMDGPU::FLAT_SCR_LO: return "flat_scratch_lo"; case AMDGPU::FLAT_SCR_HI: return "flat_scratch_hi"; default: break; } const TargetRegisterClass *RC = getMinimalPhysRegClass(Reg); unsigned Size = getRegSizeInBits(*RC); unsigned AltName = AMDGPU::NoRegAltName; Loading
llvm/lib/Target/AMDGPU/SIRegisterInfo.td +1 −1 Original line number Diff line number Diff line Loading @@ -171,7 +171,7 @@ foreach Index = 0-15 in { multiclass FLAT_SCR_LOHI_m <string n, bits<16> ci_e, bits<16> vi_e> { def _ci : SIReg<n, ci_e>; def _vi : SIReg<n, vi_e>; def "" : SIReg<"", 0>; def "" : SIReg<n, 0>; } class FlatReg <Register lo, Register hi, bits<16> encoding> : Loading