Loading llvm/lib/Target/X86/X86ISelLowering.cpp +10 −2 Original line number Diff line number Diff line Loading @@ -5471,11 +5471,19 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const { // FIXME: pshufb, blends, shifts. if (VT.getVectorNumElements() == 2 || ShuffleVectorSDNode::isSplatMask(&M[0], VT) || isPSHUFHWMask(M, VT) || isPSHUFLWMask(M, VT) || isPALIGNRMask(M, VT, Subtarget->hasSSSE3())) return Op; if (isPSHUFHWMask(M, VT)) return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1, X86::getShufflePSHUFHWImmediate(SVOp), DAG); if (isPSHUFLWMask(M, VT)) return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1, X86::getShufflePSHUFLWImmediate(SVOp), DAG); if (isSHUFPMask(M, VT)) { unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp); if (VT == MVT::v4f32 || VT == MVT::v4i32) Loading Loading
llvm/lib/Target/X86/X86ISelLowering.cpp +10 −2 Original line number Diff line number Diff line Loading @@ -5471,11 +5471,19 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const { // FIXME: pshufb, blends, shifts. if (VT.getVectorNumElements() == 2 || ShuffleVectorSDNode::isSplatMask(&M[0], VT) || isPSHUFHWMask(M, VT) || isPSHUFLWMask(M, VT) || isPALIGNRMask(M, VT, Subtarget->hasSSSE3())) return Op; if (isPSHUFHWMask(M, VT)) return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1, X86::getShufflePSHUFHWImmediate(SVOp), DAG); if (isPSHUFLWMask(M, VT)) return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1, X86::getShufflePSHUFLWImmediate(SVOp), DAG); if (isSHUFPMask(M, VT)) { unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp); if (VT == MVT::v4f32 || VT == MVT::v4i32) Loading