Commit 94b2adcf authored by Tom Stellard's avatar Tom Stellard
Browse files

Merging r266152: 

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r266152 | thomas.stellard | 2016-04-12 16:57:30 -0700 (Tue, 12 Apr 2016) | 13 lines

AMDGPU/SI: Fix spilling of 96-bit registers

Summary:
It seems like this was broken in r252327.  I thought we had test cases
for this, but it's really hard to tirgger spills of this exact register
size since they aren't used very much.

Reviewers: arsenm, nhaehnle

Subscribers: nhaehnle, arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D19021

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llvm-svn: 271735
parent 6b46e17b

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

+4 −0
Original line number Diff line number Diff line
@@ -525,6 +525,8 @@ static unsigned getVGPRSpillSaveOpcode(unsigned Size) { 
    return AMDGPU::SI_SPILL_V32_SAVE;

  case 8:

    return AMDGPU::SI_SPILL_V64_SAVE;

  case 12:

    return AMDGPU::SI_SPILL_V96_SAVE;

  case 16:

    return AMDGPU::SI_SPILL_V128_SAVE;

  case 32:
@@ -616,6 +618,8 @@ static unsigned getVGPRSpillRestoreOpcode(unsigned Size) { 
    return AMDGPU::SI_SPILL_V32_RESTORE;

  case 8:

    return AMDGPU::SI_SPILL_V64_RESTORE;

  case 12:

    return AMDGPU::SI_SPILL_V96_RESTORE;

  case 16:

    return AMDGPU::SI_SPILL_V128_RESTORE;

  case 32: