Commit 8e8a75ad authored by Fangrui Song's avatar Fangrui Song
Browse files

[TargetRegisterInfo] Default trackLivenessAfterRegAlloc() to true 

Except AMDGPU/R600RegisterInfo (a bunch of MIR tests seem to have
problems), every target overrides it with true. PostMachineScheduler
requires livein information. Not providing it can cause assertion
failures in ScheduleDAGInstrs::addSchedBarrierDeps().
parent 84217ad6

llvm/include/llvm/CodeGen/TargetRegisterInfo.h

+1 −1
Original line number Diff line number Diff line
@@ -855,7 +855,7 @@ public: 


  /// Returns true if the live-ins should be tracked after register allocation.

  virtual bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const {

    return false;

    return true;

  }



  /// True if the stack can be realigned for the target.

llvm/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp

+0 −3
Original line number Diff line number Diff line
@@ -823,9 +823,6 @@ bool FalkorHWPFFix::runOnMachineFunction(MachineFunction &Fn) { 
  TII = static_cast<const AArch64InstrInfo *>(ST.getInstrInfo());

  TRI = ST.getRegisterInfo();



  assert(TRI->trackLivenessAfterRegAlloc(Fn) &&

         "Register liveness not available!");



  MachineLoopInfo &LI = getAnalysis<MachineLoopInfo>();



  Modified = false;

llvm/lib/Target/AArch64/AArch64RegisterInfo.h

+0 −4
Original line number Diff line number Diff line
@@ -118,10 +118,6 @@ public: 
  unsigned getRegPressureLimit(const TargetRegisterClass *RC,

                               MachineFunction &MF) const override;



  bool trackLivenessAfterRegAlloc(const MachineFunction&) const override {

    return true;

  }



  unsigned getLocalAddressRegister(const MachineFunction &MF) const;

};

llvm/lib/Target/AMDGPU/R600RegisterInfo.h

+4 −0
Original line number Diff line number Diff line
@@ -40,6 +40,10 @@ struct R600RegisterInfo final : public R600GenRegisterInfo { 
  const RegClassWeight &

    getRegClassWeight(const TargetRegisterClass *RC) const override;



  bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override {

    return false;

  }



  // \returns true if \p Reg can be defined in one ALU clause and used in

  // another.

  bool isPhysRegLiveAcrossClauses(unsigned Reg) const;

llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp

+0 −5
Original line number Diff line number Diff line
@@ -305,11 +305,6 @@ bool SIRegisterInfo::requiresVirtualBaseRegisters( 
  return true;

}



bool SIRegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const {

  // This helps catch bugs as verifier errors.

  return true;

}



int64_t SIRegisterInfo::getMUBUFInstrOffset(const MachineInstr *MI) const {

  assert(SIInstrInfo::isMUBUF(*MI));