Commit 8da04022 authored by Craig Topper's avatar Craig Topper
Browse files

[X86] Disable combineConcatVectors for vXi1 vectors. 

I'm not convinced the code this calls is properly vetted for
vXi1 vectors. Experimental vector widening legalization testing
for D55251 is now hitting an assertion failure inside
EltsFromConsecutiveLoads. This is occurring from a v2i1 load
having a store size different than its VT size. Hopefully
this commit will keep such issues from happening.

llvm-svn: 366405
parent 4f93b8b5

llvm/lib/Target/X86/X86ISelLowering.cpp

+4 −0
Original line number Diff line number Diff line
@@ -43730,6 +43730,10 @@ static SDValue combineConcatVectors(SDNode *N, SelectionDAG &DAG, 
  EVT SrcVT = N->getOperand(0).getValueType();

  const TargetLowering &TLI = DAG.getTargetLoweringInfo();













  // Don't do anything for i1 vectors.













  if (VT.getVectorElementType() == MVT::i1)













    return SDValue();



























  if (Subtarget.hasAVX() && TLI.isTypeLegal(VT) && TLI.isTypeLegal(SrcVT)) {















    SmallVector<SDValue, 4> Ops(N->op_begin(), N->op_end());















    if (SDValue R = combineConcatVectorOps(SDLoc(N), VT.getSimpleVT(), Ops, DAG,

























llvm/test/CodeGen/X86/avx512vl-intrinsics-upgrade.ll



+112
−116




























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