Loading llvm/lib/Target/X86/X86ISelLowering.cpp +5 −2 Original line number Diff line number Diff line Loading @@ -2675,7 +2675,8 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) { return Op; } if (X86::isSHUFPMask(PermMask.Val)) if (X86::isSHUFPMask(PermMask.Val) && MVT::getSizeInBits(VT) != 64) // Don't do this for MMX. return Op; // Handle v8i16 shuffle high / low shuffle node pair. Loading Loading @@ -2712,7 +2713,9 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) { } } if (NumElems == 4) { if (NumElems == 4 && // Don't do this for MMX. MVT::getSizeInBits(VT) != 64) { MVT::ValueType MaskVT = PermMask.getValueType(); MVT::ValueType MaskEVT = MVT::getVectorBaseType(MaskVT); SmallVector<std::pair<int, int>, 8> Locs; Loading Loading
llvm/lib/Target/X86/X86ISelLowering.cpp +5 −2 Original line number Diff line number Diff line Loading @@ -2675,7 +2675,8 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) { return Op; } if (X86::isSHUFPMask(PermMask.Val)) if (X86::isSHUFPMask(PermMask.Val) && MVT::getSizeInBits(VT) != 64) // Don't do this for MMX. return Op; // Handle v8i16 shuffle high / low shuffle node pair. Loading Loading @@ -2712,7 +2713,9 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) { } } if (NumElems == 4) { if (NumElems == 4 && // Don't do this for MMX. MVT::getSizeInBits(VT) != 64) { MVT::ValueType MaskVT = PermMask.getValueType(); MVT::ValueType MaskEVT = MVT::getVectorBaseType(MaskVT); SmallVector<std::pair<int, int>, 8> Locs; Loading