Commit 85debca4 authored by Bill Wendling's avatar Bill Wendling
Browse files

In LLVM 2.9, the GHC calling convention is only supported on x86-32, 

x86-64. We (GHC team) would like this patch included as we've recently
added support to GHC for the ARM platform.
Patch by David Terei!

llvm-svn: 142820
parent 68fa59d9

llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp

+14 −1
Original line number Diff line number Diff line
@@ -63,6 +63,13 @@ ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii, 


const unsigned*

ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {

  bool ghcCall = false;



  if (MF) {

    const Function *F = MF->getFunction();

    ghcCall = (F ? F->getCallingConv() == CallingConv::GHC : false);

  }



  static const unsigned CalleeSavedRegs[] = {

    ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8,

    ARM::R7, ARM::R6,  ARM::R5,  ARM::R4,
@@ -82,7 +89,13 @@ ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 
    ARM::D11, ARM::D10, ARM::D9,  ARM::D8,

    0

  };

  return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs;



  static const unsigned GhcCalleeSavedRegs[] = {

    0

  };



  return ghcCall ? GhcCalleeSavedRegs :

         STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs;

}



BitVector ARMBaseRegisterInfo::

llvm/lib/Target/ARM/ARMCallingConv.td

+19 −0
Original line number Diff line number Diff line
@@ -82,6 +82,25 @@ def RetFastCC_ARM_APCS : CallingConv<[ 
  CCDelegateTo<RetCC_ARM_APCS>

]>;



//===----------------------------------------------------------------------===//

// ARM APCS Calling Convention for GHC

//===----------------------------------------------------------------------===//



def CC_ARM_APCS_GHC : CallingConv<[

  // Handle all vector types as either f64 or v2f64.

  CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,

  CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,



  CCIfType<[v2f64], CCAssignToReg<[Q4, Q5]>>,

  CCIfType<[f64], CCAssignToReg<[D8, D9, D10, D11]>>,

  CCIfType<[f32], CCAssignToReg<[S16, S17, S18, S19, S20, S21, S22, S23]>>,



  // Promote i8/i16 arguments to i32.

  CCIfType<[i8, i16], CCPromoteToType<i32>>,



  // Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, SpLim

  CCIfType<[i32], CCAssignToReg<[R4, R5, R6, R7, R8, R9, R10, R11]>>

]>;



//===----------------------------------------------------------------------===//

// ARM AAPCS (EABI) Calling Convention, common parts

llvm/lib/Target/ARM/ARMFastISel.cpp

+5 −0
Original line number Diff line number Diff line
@@ -1548,6 +1548,11 @@ CCAssignFn *ARMFastISel::CCAssignFnForCall(CallingConv::ID CC, bool Return) { 
    return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);

  case CallingConv::ARM_APCS:

    return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);

  case CallingConv::GHC:

    if (Return)

      llvm_unreachable("Can't return in GHC call convention");

    else

      return CC_ARM_APCS_GHC;

  }

}

llvm/lib/Target/ARM/ARMFrameLowering.cpp

+10 −0
Original line number Diff line number Diff line
@@ -15,6 +15,8 @@ 
#include "ARMBaseInstrInfo.h"

#include "ARMBaseRegisterInfo.h"

#include "ARMMachineFunctionInfo.h"

#include "llvm/CallingConv.h"

#include "llvm/Function.h"

#include "MCTargetDesc/ARMAddressingModes.h"

#include "llvm/CodeGen/MachineFrameInfo.h"

#include "llvm/CodeGen/MachineFunction.h"
@@ -139,6 +141,10 @@ void ARMFrameLowering::emitPrologue(MachineFunction &MF) const { 
  unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;

  int FramePtrSpillFI = 0;



  // All calls are tail calls in GHC calling conv, and functions have no prologue/epilogue.

  if (MF.getFunction()->getCallingConv() == CallingConv::GHC)

    return;



  // Allocate the vararg register save area. This is not counted in NumBytes.

  if (VARegSaveSize)

    emitSPUpdate(isARM, MBB, MBBI, dl, TII, -VARegSaveSize,
@@ -326,6 +332,10 @@ void ARMFrameLowering::emitEpilogue(MachineFunction &MF, 
  int NumBytes = (int)MFI->getStackSize();

  unsigned FramePtr = RegInfo->getFrameRegister(MF);



  // All calls are tail calls in GHC calling conv, and functions have no prologue/epilogue.

  if (MF.getFunction()->getCallingConv() == CallingConv::GHC)

    return;



  if (!AFI->hasStackFrame()) {

    if (NumBytes != 0)

      emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);

llvm/lib/Target/ARM/ARMISelLowering.cpp

+2 −0
Original line number Diff line number Diff line
@@ -1091,6 +1091,8 @@ CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC, 
    return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);

  case CallingConv::ARM_APCS:

    return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);

  case CallingConv::GHC:

    return (Return ? RetCC_ARM_APCS : CC_ARM_APCS_GHC);

  }

}