Commit 8505c3b1 authored by Simon Pilgrim's avatar Simon Pilgrim
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[DAG] canCreateUndefOrPoison - remove AssertSext/AssertZext assumption that... 

[DAG] canCreateUndefOrPoison - remove AssertSext/AssertZext assumption that they never create undef/poison

We need to assume that we generate poison if the assertions failed

Fixes #66603
parent 309e41dd

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

+0 −2
Original line number Diff line number Diff line
@@ -5011,8 +5011,6 @@ bool SelectionDAG::canCreateUndefOrPoison(SDValue Op, const APInt &DemandedElts, 


  unsigned Opcode = Op.getOpcode();

  switch (Opcode) {

  case ISD::AssertSext:

  case ISD::AssertZext:

  case ISD::FREEZE:

  case ISD::CONCAT_VECTORS:

  case ISD::INSERT_SUBVECTOR:

llvm/test/CodeGen/AArch64/pr66603.ll

+3 −1
Original line number Diff line number Diff line 
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3

; RUN: llc < %s -mtriple=aarch64-- -verify-machineinstrs | FileCheck %s



; Don't fold freeze(assertsext(x)) -> assertsext(freeze(x))

define i32 @PR66603(double %x) nounwind {

; CHECK-LABEL: PR66603:

; CHECK:       // %bb.0:

; CHECK-NEXT:    fcvtzs w0, d0

; CHECK-NEXT:    fcvtzs w8, d0

; CHECK-NEXT:    sxtb w0, w8

; CHECK-NEXT:    ret

  %as_i8 = fptosi double %x to i8

  %frozen_i8 = freeze i8 %as_i8

llvm/test/CodeGen/RISCV/pr66603.ll

+5 −0
Original line number Diff line number Diff line
@@ -2,15 +2,20 @@ 
; RUN: llc < %s -mtriple=riscv32-- -mattr=+d -verify-machineinstrs | FileCheck %s -check-prefix=RV32

; RUN: llc < %s -mtriple=riscv64-- -mattr=+d -verify-machineinstrs | FileCheck %s -check-prefix=RV64



; Don't fold freeze(assertsext(x)) -> assertsext(freeze(x))

define i32 @PR66603(double %x) nounwind {

; RV32-LABEL: PR66603:

; RV32:       # %bb.0:

; RV32-NEXT:    fcvt.w.d a0, fa0, rtz

; RV32-NEXT:    slli a0, a0, 24

; RV32-NEXT:    srai a0, a0, 24

; RV32-NEXT:    ret

;

; RV64-LABEL: PR66603:

; RV64:       # %bb.0:

; RV64-NEXT:    fcvt.l.d a0, fa0, rtz

; RV64-NEXT:    slli a0, a0, 56

; RV64-NEXT:    srai a0, a0, 56

; RV64-NEXT:    ret

  %as_i8 = fptosi double %x to i8

  %frozen_i8 = freeze i8 %as_i8

llvm/test/CodeGen/RISCV/rv64zbb.ll

+1 −1
Original line number Diff line number Diff line
@@ -1422,7 +1422,7 @@ define i32 @abs_i32(i32 %x) { 
define signext i32 @abs_i32_sext(i32 signext %x) {

; RV64I-LABEL: abs_i32_sext:

; RV64I:       # %bb.0:

; RV64I-NEXT:    srai a1, a0, 31

; RV64I-NEXT:    sraiw a1, a0, 31

; RV64I-NEXT:    xor a0, a0, a1

; RV64I-NEXT:    subw a0, a0, a1

; RV64I-NEXT:    ret