Commit 80b627d6 authored by Matt Arsenault's avatar Matt Arsenault Committed by Matt Arsenault
Browse files

AMDGPU/GlobalISel: Fix handling of G_ANYEXT with s1 source 

We were letting G_ANYEXT with a vcc register bank through, which was
incorrect and would select to an invalid copy. Fix this up like G_ZEXT
and G_SEXT. Also drop old code to fixup the non-boolean case in
RegBankSelect. We now have to perform that expansion during selection,
so there's no benefit to doing it during RegBankSelect.
parent c460dc6e

llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

+19 −36
Original line number Diff line number Diff line
@@ -220,7 +220,7 @@ unsigned AMDGPURegisterBankInfo::copyCost(const RegisterBank &Dst, 
                                          unsigned Size) const {

  // TODO: Should there be a UniformVGPRRegBank which can use readfirstlane?

  if (Dst.getID() == AMDGPU::SGPRRegBankID &&

      isVectorRegisterBank(Src)) {

      (isVectorRegisterBank(Src) || Src.getID() == AMDGPU::VCCRegBankID)) {

    return std::numeric_limits<unsigned>::max();

  }
@@ -238,9 +238,6 @@ unsigned AMDGPURegisterBankInfo::copyCost(const RegisterBank &Dst, 
       Src.getID() == AMDGPU::VCCRegBankID))

    return std::numeric_limits<unsigned>::max();



  if (Src.getID() == AMDGPU::VCCRegBankID)

    return std::numeric_limits<unsigned>::max();



  // There is no direct copy between AGPRs.

  if (Dst.getID() == AMDGPU::AGPRRegBankID &&

      Src.getID() == AMDGPU::AGPRRegBankID)
@@ -2252,10 +2249,13 @@ void AMDGPURegisterBankInfo::applyMappingImpl( 
    return;

  }

  case AMDGPU::G_SEXT:

  case AMDGPU::G_ZEXT: {

  case AMDGPU::G_ZEXT:

  case AMDGPU::G_ANYEXT: {

    Register SrcReg = MI.getOperand(1).getReg();

    LLT SrcTy = MRI.getType(SrcReg);

    bool Signed = Opc == AMDGPU::G_SEXT;

    const bool Signed = Opc == AMDGPU::G_SEXT;



    assert(empty(OpdMapper.getVRegs(1)));



    MachineIRBuilder B(MI);

    const RegisterBank *SrcBank =
@@ -2282,9 +2282,12 @@ void AMDGPURegisterBankInfo::applyMappingImpl( 
        auto ShiftAmt = B.buildConstant(S32, 31);

        MRI.setRegBank(ShiftAmt.getReg(0), *SrcBank);

        B.buildAShr(DefRegs[1], DefRegs[0], ShiftAmt);

      } else {

      } else if (Opc == AMDGPU::G_ZEXT) {

        B.buildZExtOrTrunc(DefRegs[0], SrcReg);

        B.buildConstant(DefRegs[1], 0);

      } else {

        B.buildAnyExtOrTrunc(DefRegs[0], SrcReg);

        B.buildUndef(DefRegs[1]);

      }



      MRI.setRegBank(DstReg, *SrcBank);
@@ -2295,6 +2298,9 @@ void AMDGPURegisterBankInfo::applyMappingImpl( 
    if (SrcTy != LLT::scalar(1))

      return;



    // It is not legal to have a legalization artifact with a VCC source. Rather

    // than introducing a copy, insert the selcet we would have to select the

    // copy to.

    if (SrcBank == &AMDGPU::VCCRegBank) {

      SmallVector<Register, 2> DefRegs(OpdMapper.getVRegs(0));
@@ -2329,24 +2335,7 @@ void AMDGPURegisterBankInfo::applyMappingImpl( 
      return;

    }



    // Fixup the case with an s1 src that isn't a condition register. Use shifts

    // instead of introducing a compare to avoid an unnecessary condition

    // register (and since there's no scalar 16-bit compares).

    auto Ext = B.buildAnyExt(DstTy, SrcReg);

    auto ShiftAmt = B.buildConstant(LLT::scalar(32), DstTy.getSizeInBits() - 1);

    auto Shl = B.buildShl(DstTy, Ext, ShiftAmt);



    if (MI.getOpcode() == AMDGPU::G_SEXT)

      B.buildAShr(DstReg, Shl, ShiftAmt);

    else

      B.buildLShr(DstReg, Shl, ShiftAmt);



    MRI.setRegBank(DstReg, *SrcBank);

    MRI.setRegBank(Ext.getReg(0), *SrcBank);

    MRI.setRegBank(ShiftAmt.getReg(0), *SrcBank);

    MRI.setRegBank(Shl.getReg(0), *SrcBank);

    MI.eraseFromParent();

    return;

    break;

  }

  case AMDGPU::G_BUILD_VECTOR:

  case AMDGPU::G_BUILD_VECTOR_TRUNC: {
@@ -3423,17 +3412,11 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { 
      break;

    }



    // TODO: Should anyext be split into 32-bit part as well?

    if (MI.getOpcode() == AMDGPU::G_ANYEXT) {

      OpdsMapping[0] = AMDGPU::getValueMapping(DstBank, DstSize);

      OpdsMapping[1] = AMDGPU::getValueMapping(SrcBank->getID(), SrcSize);

    } else {

    // Scalar extend can use 64-bit BFE, but VGPRs require extending to

    // 32-bits, and then to 64.

    OpdsMapping[0] = AMDGPU::getValueMappingSGPR64Only(DstBank, DstSize);

    OpdsMapping[1] = AMDGPU::getValueMappingSGPR64Only(SrcBank->getID(),

                                                       SrcSize);

    }

    break;

  }

  case AMDGPU::G_FCMP: {

llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll

+220 −326

File changed.

Preview size limit exceeded, changes collapsed.

llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-anyext.mir

+19 −6
Original line number Diff line number Diff line
@@ -22,10 +22,12 @@ legalized: true 


body: |

  bb.0:

    liveins: $vgpr0_vgpr1

    liveins: $vgpr0

    ; CHECK-LABEL: name: anyext_s32_to_s64_v

    ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

    ; CHECK: [[ANYEXT:%[0-9]+]]:vgpr(s64) = G_ANYEXT [[COPY]](s32)

    ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)

    ; CHECK: [[DEF:%[0-9]+]]:vgpr(s32) = G_IMPLICIT_DEF

    ; CHECK: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[COPY1]](s32), [[DEF]](s32)

    %0:_(s32) = COPY $vgpr0

    %1:_(s64) = G_ANYEXT %0

...
@@ -98,7 +100,10 @@ body: | 
    ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

    ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1

    ; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]

    ; CHECK: [[ANYEXT:%[0-9]+]]:vgpr(s16) = G_ANYEXT [[ICMP]](s1)

    ; CHECK: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1

    ; CHECK: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

    ; CHECK: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[C]], [[C1]]

    ; CHECK: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[SELECT]](s32)

    %0:_(s32) = COPY $vgpr0

    %1:_(s32) = COPY $vgpr1

    %2:_(s1) = G_ICMP intpred(eq), %0, %1
@@ -116,7 +121,9 @@ body: | 
    ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

    ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1

    ; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]

    ; CHECK: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[ICMP]](s1)

    ; CHECK: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1

    ; CHECK: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

    ; CHECK: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[C]], [[C1]]

    %0:_(s32) = COPY $vgpr0

    %1:_(s32) = COPY $vgpr1

    %2:_(s1) = G_ICMP intpred(eq), %0, %1
@@ -134,7 +141,11 @@ body: | 
    ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

    ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1

    ; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]

    ; CHECK: [[ANYEXT:%[0-9]+]]:vgpr(s64) = G_ANYEXT [[ICMP]](s1)

    ; CHECK: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1

    ; CHECK: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0

    ; CHECK: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[C]], [[C1]]

    ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[SELECT]](s32)

    ; CHECK: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[SELECT]](s32), [[COPY2]](s32)

    %0:_(s32) = COPY $vgpr0

    %1:_(s32) = COPY $vgpr1

    %2:_(s1) = G_ICMP intpred(eq), %0, %1
@@ -231,7 +242,9 @@ body: | 
    ; CHECK-LABEL: name: anyext_s1_to_s64_vgpr

    ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

    ; CHECK: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)

    ; CHECK: [[ANYEXT:%[0-9]+]]:vgpr(s64) = G_ANYEXT [[TRUNC]](s1)

    ; CHECK: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[TRUNC]](s1)

    ; CHECK: [[DEF:%[0-9]+]]:vgpr(s32) = G_IMPLICIT_DEF

    ; CHECK: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[ANYEXT]](s32), [[DEF]](s32)

    %0:_(s32) = COPY $vgpr0

    %1:_(s1) = G_TRUNC %0

    %2:_(s64) = G_ANYEXT %1

llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext.mir

+8 −32
Original line number Diff line number Diff line
@@ -61,10 +61,7 @@ body: | 
    ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1

    ; CHECK: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]

    ; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)

    ; CHECK: [[ANYEXT:%[0-9]+]]:sgpr(s16) = G_ANYEXT [[TRUNC]](s1)

    ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 15

    ; CHECK: [[SHL:%[0-9]+]]:sgpr(s16) = G_SHL [[ANYEXT]], [[C]](s32)

    ; CHECK: [[ASHR:%[0-9]+]]:sgpr(s16) = G_ASHR [[SHL]], [[C]](s32)

    ; CHECK: [[SEXT:%[0-9]+]]:sgpr(s16) = G_SEXT [[TRUNC]](s1)

    %0:_(s32) = COPY $sgpr0

    %1:_(s32) = COPY $sgpr1

    %2:_(s1) = G_ICMP intpred(eq), %0, %1
@@ -83,10 +80,7 @@ body: | 
    ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1

    ; CHECK: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]

    ; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)

    ; CHECK: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC]](s1)

    ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 31

    ; CHECK: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[ANYEXT]], [[C]](s32)

    ; CHECK: [[ASHR:%[0-9]+]]:sgpr(s32) = G_ASHR [[SHL]], [[C]](s32)

    ; CHECK: [[SEXT:%[0-9]+]]:sgpr(s32) = G_SEXT [[TRUNC]](s1)

    %0:_(s32) = COPY $sgpr0

    %1:_(s32) = COPY $sgpr1

    %2:_(s1) = G_ICMP intpred(eq), %0, %1
@@ -105,10 +99,7 @@ body: | 
    ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1

    ; CHECK: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]

    ; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)

    ; CHECK: [[ANYEXT:%[0-9]+]]:sgpr(s64) = G_ANYEXT [[TRUNC]](s1)

    ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 63

    ; CHECK: [[SHL:%[0-9]+]]:sgpr(s64) = G_SHL [[ANYEXT]], [[C]](s32)

    ; CHECK: [[ASHR:%[0-9]+]]:sgpr(s64) = G_ASHR [[SHL]], [[C]](s32)

    ; CHECK: [[SEXT:%[0-9]+]]:sgpr(s64) = G_SEXT [[TRUNC]](s1)

    %0:_(s32) = COPY $sgpr0

    %1:_(s32) = COPY $sgpr1

    %2:_(s1) = G_ICMP intpred(eq), %0, %1
@@ -188,10 +179,7 @@ body: | 
    ; CHECK-LABEL: name: sext_s1_to_s16_sgpr

    ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0

    ; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)

    ; CHECK: [[ANYEXT:%[0-9]+]]:sgpr(s16) = G_ANYEXT [[TRUNC]](s1)

    ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 15

    ; CHECK: [[SHL:%[0-9]+]]:sgpr(s16) = G_SHL [[ANYEXT]], [[C]](s32)

    ; CHECK: [[ASHR:%[0-9]+]]:sgpr(s16) = G_ASHR [[SHL]], [[C]](s32)

    ; CHECK: [[SEXT:%[0-9]+]]:sgpr(s16) = G_SEXT [[TRUNC]](s1)

    %0:_(s32) = COPY $sgpr0

    %1:_(s1) = G_TRUNC %0

    %2:_(s16) = G_SEXT %1
@@ -207,10 +195,7 @@ body: | 
    ; CHECK-LABEL: name: sext_s1_to_s32_sgpr

    ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0

    ; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)

    ; CHECK: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC]](s1)

    ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 31

    ; CHECK: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[ANYEXT]], [[C]](s32)

    ; CHECK: [[ASHR:%[0-9]+]]:sgpr(s32) = G_ASHR [[SHL]], [[C]](s32)

    ; CHECK: [[SEXT:%[0-9]+]]:sgpr(s32) = G_SEXT [[TRUNC]](s1)

    %0:_(s32) = COPY $sgpr0

    %1:_(s1) = G_TRUNC %0

    %2:_(s32) = G_SEXT %1
@@ -226,10 +211,7 @@ body: | 
    ; CHECK-LABEL: name: sext_s1_to_s64_sgpr

    ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0

    ; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)

    ; CHECK: [[ANYEXT:%[0-9]+]]:sgpr(s64) = G_ANYEXT [[TRUNC]](s1)

    ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 63

    ; CHECK: [[SHL:%[0-9]+]]:sgpr(s64) = G_SHL [[ANYEXT]], [[C]](s32)

    ; CHECK: [[ASHR:%[0-9]+]]:sgpr(s64) = G_ASHR [[SHL]], [[C]](s32)

    ; CHECK: [[SEXT:%[0-9]+]]:sgpr(s64) = G_SEXT [[TRUNC]](s1)

    %0:_(s32) = COPY $sgpr0

    %1:_(s1) = G_TRUNC %0

    %2:_(s64) = G_SEXT %1
@@ -245,10 +227,7 @@ body: | 
    ; CHECK-LABEL: name: sext_s1_to_s16_vgpr

    ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

    ; CHECK: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)

    ; CHECK: [[ANYEXT:%[0-9]+]]:vgpr(s16) = G_ANYEXT [[TRUNC]](s1)

    ; CHECK: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 15

    ; CHECK: [[SHL:%[0-9]+]]:vgpr(s16) = G_SHL [[ANYEXT]], [[C]](s32)

    ; CHECK: [[ASHR:%[0-9]+]]:vgpr(s16) = G_ASHR [[SHL]], [[C]](s32)

    ; CHECK: [[SEXT:%[0-9]+]]:vgpr(s16) = G_SEXT [[TRUNC]](s1)

    %0:_(s32) = COPY $vgpr0

    %1:_(s1) = G_TRUNC %0

    %2:_(s16) = G_SEXT %1
@@ -264,10 +243,7 @@ body: | 
    ; CHECK-LABEL: name: sext_s1_to_s32_vgpr

    ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

    ; CHECK: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)

    ; CHECK: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[TRUNC]](s1)

    ; CHECK: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 31

    ; CHECK: [[SHL:%[0-9]+]]:vgpr(s32) = G_SHL [[ANYEXT]], [[C]](s32)

    ; CHECK: [[ASHR:%[0-9]+]]:vgpr(s32) = G_ASHR [[SHL]], [[C]](s32)

    ; CHECK: [[SEXT:%[0-9]+]]:vgpr(s32) = G_SEXT [[TRUNC]](s1)

    %0:_(s32) = COPY $vgpr0

    %1:_(s1) = G_TRUNC %0

    %2:_(s32) = G_SEXT %1

llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zext.mir

+8 −32
Original line number Diff line number Diff line
@@ -60,10 +60,7 @@ body: | 
    ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1

    ; CHECK: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]

    ; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)

    ; CHECK: [[ANYEXT:%[0-9]+]]:sgpr(s16) = G_ANYEXT [[TRUNC]](s1)

    ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 15

    ; CHECK: [[SHL:%[0-9]+]]:sgpr(s16) = G_SHL [[ANYEXT]], [[C]](s32)

    ; CHECK: [[LSHR:%[0-9]+]]:sgpr(s16) = G_LSHR [[SHL]], [[C]](s32)

    ; CHECK: [[ZEXT:%[0-9]+]]:sgpr(s16) = G_ZEXT [[TRUNC]](s1)

    %0:_(s32) = COPY $sgpr0

    %1:_(s32) = COPY $sgpr1

    %2:_(s1) = G_ICMP intpred(eq), %0, %1
@@ -82,10 +79,7 @@ body: | 
    ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1

    ; CHECK: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]

    ; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)

    ; CHECK: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC]](s1)

    ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 31

    ; CHECK: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[ANYEXT]], [[C]](s32)

    ; CHECK: [[LSHR:%[0-9]+]]:sgpr(s32) = G_LSHR [[SHL]], [[C]](s32)

    ; CHECK: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)

    %0:_(s32) = COPY $sgpr0

    %1:_(s32) = COPY $sgpr1

    %2:_(s1) = G_ICMP intpred(eq), %0, %1
@@ -104,10 +98,7 @@ body: | 
    ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1

    ; CHECK: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]

    ; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)

    ; CHECK: [[ANYEXT:%[0-9]+]]:sgpr(s64) = G_ANYEXT [[TRUNC]](s1)

    ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 63

    ; CHECK: [[SHL:%[0-9]+]]:sgpr(s64) = G_SHL [[ANYEXT]], [[C]](s32)

    ; CHECK: [[LSHR:%[0-9]+]]:sgpr(s64) = G_LSHR [[SHL]], [[C]](s32)

    ; CHECK: [[ZEXT:%[0-9]+]]:sgpr(s64) = G_ZEXT [[TRUNC]](s1)

    %0:_(s32) = COPY $sgpr0

    %1:_(s32) = COPY $sgpr1

    %2:_(s1) = G_ICMP intpred(eq), %0, %1
@@ -187,10 +178,7 @@ body: | 
    ; CHECK-LABEL: name: zext_s1_to_s16_sgpr

    ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0

    ; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)

    ; CHECK: [[ANYEXT:%[0-9]+]]:sgpr(s16) = G_ANYEXT [[TRUNC]](s1)

    ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 15

    ; CHECK: [[SHL:%[0-9]+]]:sgpr(s16) = G_SHL [[ANYEXT]], [[C]](s32)

    ; CHECK: [[LSHR:%[0-9]+]]:sgpr(s16) = G_LSHR [[SHL]], [[C]](s32)

    ; CHECK: [[ZEXT:%[0-9]+]]:sgpr(s16) = G_ZEXT [[TRUNC]](s1)

    %0:_(s32) = COPY $sgpr0

    %1:_(s1) = G_TRUNC %0

    %2:_(s16) = G_ZEXT %1
@@ -206,10 +194,7 @@ body: | 
    ; CHECK-LABEL: name: zext_s1_to_s32_sgpr

    ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0

    ; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)

    ; CHECK: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC]](s1)

    ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 31

    ; CHECK: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[ANYEXT]], [[C]](s32)

    ; CHECK: [[LSHR:%[0-9]+]]:sgpr(s32) = G_LSHR [[SHL]], [[C]](s32)

    ; CHECK: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)

    %0:_(s32) = COPY $sgpr0

    %1:_(s1) = G_TRUNC %0

    %2:_(s32) = G_ZEXT %1
@@ -225,10 +210,7 @@ body: | 
    ; CHECK-LABEL: name: zext_s1_to_s64_sgpr

    ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0

    ; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)

    ; CHECK: [[ANYEXT:%[0-9]+]]:sgpr(s64) = G_ANYEXT [[TRUNC]](s1)

    ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 63

    ; CHECK: [[SHL:%[0-9]+]]:sgpr(s64) = G_SHL [[ANYEXT]], [[C]](s32)

    ; CHECK: [[LSHR:%[0-9]+]]:sgpr(s64) = G_LSHR [[SHL]], [[C]](s32)

    ; CHECK: [[ZEXT:%[0-9]+]]:sgpr(s64) = G_ZEXT [[TRUNC]](s1)

    %0:_(s32) = COPY $sgpr0

    %1:_(s1) = G_TRUNC %0

    %2:_(s64) = G_ZEXT %1
@@ -244,10 +226,7 @@ body: | 
    ; CHECK-LABEL: name: zext_s1_to_s16_vgpr

    ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

    ; CHECK: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)

    ; CHECK: [[ANYEXT:%[0-9]+]]:vgpr(s16) = G_ANYEXT [[TRUNC]](s1)

    ; CHECK: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 15

    ; CHECK: [[SHL:%[0-9]+]]:vgpr(s16) = G_SHL [[ANYEXT]], [[C]](s32)

    ; CHECK: [[LSHR:%[0-9]+]]:vgpr(s16) = G_LSHR [[SHL]], [[C]](s32)

    ; CHECK: [[ZEXT:%[0-9]+]]:vgpr(s16) = G_ZEXT [[TRUNC]](s1)

    %0:_(s32) = COPY $vgpr0

    %1:_(s1) = G_TRUNC %0

    %2:_(s16) = G_ZEXT %1
@@ -263,10 +242,7 @@ body: | 
    ; CHECK-LABEL: name: zext_s1_to_s32_vgpr

    ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0

    ; CHECK: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)

    ; CHECK: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[TRUNC]](s1)

    ; CHECK: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 31

    ; CHECK: [[SHL:%[0-9]+]]:vgpr(s32) = G_SHL [[ANYEXT]], [[C]](s32)

    ; CHECK: [[LSHR:%[0-9]+]]:vgpr(s32) = G_LSHR [[SHL]], [[C]](s32)

    ; CHECK: [[ZEXT:%[0-9]+]]:vgpr(s32) = G_ZEXT [[TRUNC]](s1)

    %0:_(s32) = COPY $vgpr0

    %1:_(s1) = G_TRUNC %0

    %2:_(s32) = G_ZEXT %1