Commit 7ed7738a authored by Tom Stellard's avatar Tom Stellard
Browse files

Merging r202774: 

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r202774 | reid | 2014-03-03 19:33:17 -0500 (Mon, 03 Mar 2014) | 7 lines

MC: Fix Intel assembly parser for [global + offset]

We were dropping the displacement on the floor if we also had some
immediate offset.

Should fix PR19033.

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llvm-svn: 206061
parent f0092f48

llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp

+26 −14
Original line number Diff line number Diff line
@@ -1181,16 +1181,23 @@ X86AsmParser::CreateMemForInlineAsm(unsigned SegReg, const MCExpr *Disp, 
                                    unsigned Scale, SMLoc Start, SMLoc End,

                                    unsigned Size, StringRef Identifier,

                                    InlineAsmIdentifierInfo &Info){

  if (isa<MCSymbolRefExpr>(Disp)) {

  // If this is not a VarDecl then assume it is a FuncDecl or some other label

  // reference.  We need an 'r' constraint here, so we need to create register

  // operand to ensure proper matching.  Just pick a GPR based on the size of

  // a pointer.

    if (!Info.IsVarDecl) {

  if (isa<MCSymbolRefExpr>(Disp) && !Info.IsVarDecl) {

    unsigned RegNo = is64BitMode() ? X86::RBX : X86::EBX;

    return X86Operand::CreateReg(RegNo, Start, End, /*AddressOf=*/true,

                                 SMLoc(), Identifier, Info.OpDecl);

  }



  // We either have a direct symbol reference, or an offset from a symbol.  The

  // parser always puts the symbol on the LHS, so look there for size

  // calculation purposes.

  const MCBinaryExpr *BinOp = dyn_cast<MCBinaryExpr>(Disp);

  bool IsSymRef =

      isa<MCSymbolRefExpr>(BinOp ? BinOp->getLHS() : Disp);

  if (IsSymRef) {

    if (!Size) {

      Size = Info.Type * 8; // Size is in terms of bits in this context.

      if (Size)
@@ -1371,7 +1378,7 @@ X86Operand *X86AsmParser::ParseIntelBracExpression(unsigned SegReg, SMLoc Start, 
  if (ParseIntelExpression(SM, End))

    return 0;



  const MCExpr *Disp;

  const MCExpr *Disp = 0;

  if (const MCExpr *Sym = SM.getSym()) {

    // A symbolic displacement.

    Disp = Sym;
@@ -1379,9 +1386,14 @@ X86Operand *X86AsmParser::ParseIntelBracExpression(unsigned SegReg, SMLoc Start, 
      RewriteIntelBracExpression(InstInfo->AsmRewrites, SM.getSymName(),

                                 ImmDisp, SM.getImm(), BracLoc, StartInBrac,

                                 End);

  } else {

    // An immediate displacement only.   

    Disp = MCConstantExpr::Create(SM.getImm(), getContext());

  }



  if (SM.getImm() || !Disp) {

    const MCExpr *Imm = MCConstantExpr::Create(SM.getImm(), getContext());

    if (Disp)

      Disp = MCBinaryExpr::CreateAdd(Disp, Imm, getContext());

    else

      Disp = Imm;  // An immediate displacement only.

  }



  // Parse struct field access.  Intel requires a dot, but MSVC doesn't.  MSVC

llvm/test/MC/X86/intel-syntax.s

+9 −0
Original line number Diff line number Diff line
@@ -584,3 +584,12 @@ fsub ST(1) 
fsubr ST(1)

fdiv ST(1)

fdivr ST(1)



.bss

.globl _g0

.text



// CHECK: movq _g0, %rbx

// CHECK: movq _g0+8, %rcx

mov rbx, qword ptr [_g0]

mov rcx, qword ptr [_g0 + 8]