Commit 7d973307 authored by Jay Foad's avatar Jay Foad
Browse files

[AMDGPU] Fix scheduling model for V_MULLIT_F32 

This was incorrectly marked as a half rate 64-bit instruction by D45073.
parent f2d45e50

llvm/lib/Target/AMDGPU/VOP3Instructions.td

+3 −3
Original line number Diff line number Diff line
@@ -396,9 +396,6 @@ def V_LSHL_B64 : VOP3Inst <"v_lshl_b64", VOP3_Profile<VOP_I64_I64_I32>, shl>; 
def V_LSHR_B64 : VOP3Inst <"v_lshr_b64", VOP3_Profile<VOP_I64_I64_I32>, srl>;

def V_ASHR_I64 : VOP3Inst <"v_ashr_i64", VOP3_Profile<VOP_I64_I64_I32>, sra>;

} // End SubtargetPredicate = isGFX6GFX7

let SubtargetPredicate = isGFX6GFX7GFX10 in {

def V_MULLIT_F32 : VOP3Inst <"v_mullit_f32", VOP3_Profile<VOP_F32_F32_F32_F32>>;

} // End SubtargetPredicate = isGFX6GFX7GFX10



let SubtargetPredicate = isGFX8Plus in {

def V_LSHLREV_B64 : VOP3Inst <"v_lshlrev_b64", VOP3_Profile<VOP_I64_I32_I64>, lshl_rev>;
@@ -407,6 +404,9 @@ def V_ASHRREV_I64 : VOP3Inst <"v_ashrrev_i64", VOP3_Profile<VOP_I64_I32_I64>, as 
} // End SubtargetPredicate = isGFX8Plus

} // End SchedRW = [Write64Bit]



let SubtargetPredicate = isGFX6GFX7GFX10 in {

def V_MULLIT_F32 : VOP3Inst <"v_mullit_f32", VOP3_Profile<VOP_F32_F32_F32_F32>>;

} // End SubtargetPredicate = isGFX6GFX7GFX10



let SchedRW = [Write32Bit] in {

let SubtargetPredicate = isGFX8Plus in {