Unverified Commit 7b026ac8 authored by Ramkumar Ramachandra's avatar Ramkumar Ramachandra Committed by GitHub
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[VPlan] Simplify extract-lane of all single-scalars (#194838) 

Checking against vputils::isSingleScalar is sufficient for both
correctness and profitability.
parent 482d0f01

llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp

+3 −5
Original line number Diff line number Diff line
@@ -1794,11 +1794,9 @@ static void simplifyRecipe(VPSingleDefRecipe *Def, VPTypeAnalysis &TypeInfo) { 
  }



  if (match(Def, m_ExtractLastLane(m_VPValue(A))) &&

      ((isa<VPInstruction>(A) && vputils::isSingleScalar(A)) ||

       (isa<VPReplicateRecipe>(A) &&

        cast<VPReplicateRecipe>(A)->isSingleScalar())) &&

      all_of(A->users(),

             [Def, A](VPUser *U) { return U->usesScalars(A) || Def == U; })) {

      vputils::isSingleScalar(A) && all_of(A->users(), [Def, A](VPUser *U) {

        return U->usesScalars(A) || Def == U;

      })) {

    return Def->replaceAllUsesWith(A);

  }

llvm/test/Transforms/LoopVectorize/X86/replicating-load-store-costs.ll

+0 −1
Original line number Diff line number Diff line
@@ -477,7 +477,6 @@ define double @test_load_used_by_other_load_scev(ptr %ptr.a, ptr %ptr.b, ptr %pt 
; I64-NEXT:    [[TMP3:%.*]] = icmp eq i64 [[INDEX_NEXT]], 100

; I64-NEXT:    br i1 [[TMP3]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]

; I64:       [[MIDDLE_BLOCK]]:

; I64-NEXT:    [[VECTOR_RECUR_EXTRACT:%.*]] = extractelement <2 x double> [[TMP2]], i64 1

; I64-NEXT:    br label %[[SCALAR_PH:.*]]

; I64:       [[SCALAR_PH]]:

;