Commit 78873840 authored by Max Kazantsev's avatar Max Kazantsev
Browse files

[Test] Add some more symmetrical test cases for D110517 

More similar cases to see that the opt we are trying to make is generic enough.
parent b29186c0

llvm/test/Transforms/IndVarSimplify/outer_phi.ll

+197 −5
Original line number Diff line number Diff line
@@ -474,10 +474,137 @@ define i32 @test_05a(i32 %a, i32* %bp) { 
; CHECK-NEXT:    br label [[INNER:%.*]]

; CHECK:       inner:

; CHECK-NEXT:    [[IV:%.*]] = phi i32 [ [[OUTER_IV]], [[OUTER]] ], [ [[IV_NEXT:%.*]], [[INNER_BACKEDGE:%.*]] ]

; CHECK-NEXT:    [[SIGNED_COND:%.*]] = icmp ult i32 [[IV]], [[B]]

; CHECK-NEXT:    [[UNSIGNED_COND:%.*]] = icmp ult i32 [[IV]], [[B]]

; CHECK-NEXT:    br i1 [[UNSIGNED_COND]], label [[INNER_1:%.*]], label [[SIDE_EXIT:%.*]]

; CHECK:       inner.1:

; CHECK-NEXT:    [[SIGNED_COND:%.*]] = icmp slt i32 [[IV]], [[B]]

; CHECK-NEXT:    br i1 [[SIGNED_COND]], label [[INNER_BACKEDGE]], label [[SIDE_EXIT]]

; CHECK:       inner.backedge:

; CHECK-NEXT:    [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1

; CHECK-NEXT:    [[INNER_LOOP_COND:%.*]] = call i1 @cond()

; CHECK-NEXT:    br i1 [[INNER_LOOP_COND]], label [[INNER]], label [[OUTER_BACKEDGE]]

; CHECK:       outer.backedge:

; CHECK-NEXT:    [[IV_NEXT_LCSSA]] = phi i32 [ [[IV_NEXT]], [[INNER_BACKEDGE]] ]

; CHECK-NEXT:    [[OUTER_LOOP_COND:%.*]] = call i1 @cond()

; CHECK-NEXT:    br i1 [[OUTER_LOOP_COND]], label [[OUTER]], label [[EXIT:%.*]]

; CHECK:       side.exit:

; CHECK-NEXT:    ret i32 0

; CHECK:       exit:

; CHECK-NEXT:    ret i32 1

;

entry:

  %b = load i32, i32* %bp, !range !0

  br label %outer



outer:

  %outer.iv = phi i32 [0, %entry], [%iv.next, %outer.backedge]

  br label %inner





inner:

  %iv = phi i32 [%outer.iv, %outer], [%iv.next, %inner.backedge]

  %unsigned_cond = icmp ult i32 %iv, %b

  br i1 %unsigned_cond, label %inner.1, label %side.exit



inner.1:

  %signed_cond = icmp slt i32 %iv, %b

  br i1 %signed_cond, label %inner.backedge, label %side.exit



inner.backedge:

  %iv.next = add nuw nsw i32 %iv, 1

  %inner.loop.cond = call i1 @cond()

  br i1 %inner.loop.cond, label %inner, label %outer.backedge



outer.backedge:

  %outer.loop.cond = call i1 @cond()

  br i1 %outer.loop.cond, label %outer, label %exit



side.exit:

  ret i32 0



exit:

  ret i32 1

}



; Similar to test_05a, but inverted 2nd condition.

define i32 @test_05b(i32 %a, i32* %bp) {

; CHECK-LABEL: @test_05b(

; CHECK-NEXT:  entry:

; CHECK-NEXT:    [[B:%.*]] = load i32, i32* [[BP:%.*]], align 4, !range [[RNG0]]

; CHECK-NEXT:    br label [[OUTER:%.*]]

; CHECK:       outer:

; CHECK-NEXT:    [[OUTER_IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT_LCSSA:%.*]], [[OUTER_BACKEDGE:%.*]] ]

; CHECK-NEXT:    br label [[INNER:%.*]]

; CHECK:       inner:

; CHECK-NEXT:    [[IV:%.*]] = phi i32 [ [[OUTER_IV]], [[OUTER]] ], [ [[IV_NEXT:%.*]], [[INNER_BACKEDGE:%.*]] ]

; CHECK-NEXT:    [[UNSIGNED_COND:%.*]] = icmp ult i32 [[IV]], [[B]]

; CHECK-NEXT:    br i1 [[UNSIGNED_COND]], label [[INNER_1:%.*]], label [[SIDE_EXIT:%.*]]

; CHECK:       inner.1:

; CHECK-NEXT:    [[SIGNED_COND:%.*]] = icmp sgt i32 [[B]], [[IV]]

; CHECK-NEXT:    br i1 [[SIGNED_COND]], label [[INNER_BACKEDGE]], label [[SIDE_EXIT]]

; CHECK:       inner.backedge:

; CHECK-NEXT:    [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1

; CHECK-NEXT:    [[INNER_LOOP_COND:%.*]] = call i1 @cond()

; CHECK-NEXT:    br i1 [[INNER_LOOP_COND]], label [[INNER]], label [[OUTER_BACKEDGE]]

; CHECK:       outer.backedge:

; CHECK-NEXT:    [[IV_NEXT_LCSSA]] = phi i32 [ [[IV_NEXT]], [[INNER_BACKEDGE]] ]

; CHECK-NEXT:    [[OUTER_LOOP_COND:%.*]] = call i1 @cond()

; CHECK-NEXT:    br i1 [[OUTER_LOOP_COND]], label [[OUTER]], label [[EXIT:%.*]]

; CHECK:       side.exit:

; CHECK-NEXT:    ret i32 0

; CHECK:       exit:

; CHECK-NEXT:    ret i32 1

;

entry:

  %b = load i32, i32* %bp, !range !0

  br label %outer



outer:

  %outer.iv = phi i32 [0, %entry], [%iv.next, %outer.backedge]

  br label %inner





inner:

  %iv = phi i32 [%outer.iv, %outer], [%iv.next, %inner.backedge]

  %unsigned_cond = icmp ult i32 %iv, %b

  br i1 %unsigned_cond, label %inner.1, label %side.exit



inner.1:

  %signed_cond = icmp sgt i32 %b, %iv

  br i1 %signed_cond, label %inner.backedge, label %side.exit



inner.backedge:

  %iv.next = add nuw nsw i32 %iv, 1

  %inner.loop.cond = call i1 @cond()

  br i1 %inner.loop.cond, label %inner, label %outer.backedge



outer.backedge:

  %outer.loop.cond = call i1 @cond()

  br i1 %outer.loop.cond, label %outer, label %exit



side.exit:

  ret i32 0



exit:

  ret i32 1

}



; We should prove implication: iv <s b, b <s 0 => iv <u b.

; FIXME: Can remove 2nd check

define i32 @test_05c(i32 %a, i32* %bp) {

; CHECK-LABEL: @test_05c(

; CHECK-NEXT:  entry:

; CHECK-NEXT:    [[B:%.*]] = load i32, i32* [[BP:%.*]], align 4, !range [[RNG1:![0-9]+]]

; CHECK-NEXT:    br label [[OUTER:%.*]]

; CHECK:       outer:

; CHECK-NEXT:    [[OUTER_IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT_LCSSA:%.*]], [[OUTER_BACKEDGE:%.*]] ]

; CHECK-NEXT:    br label [[INNER:%.*]]

; CHECK:       inner:

; CHECK-NEXT:    [[IV:%.*]] = phi i32 [ [[OUTER_IV]], [[OUTER]] ], [ [[IV_NEXT:%.*]], [[INNER_BACKEDGE:%.*]] ]

; CHECK-NEXT:    [[SIGNED_COND:%.*]] = icmp slt i32 [[IV]], [[B]]

; CHECK-NEXT:    br i1 [[SIGNED_COND]], label [[INNER_1:%.*]], label [[SIDE_EXIT:%.*]]

; CHECK:       inner.1:

; CHECK-NEXT:    [[UNSIGNED_COND:%.*]] = icmp slt i32 [[IV]], [[B]]

; CHECK-NEXT:    [[UNSIGNED_COND:%.*]] = icmp ult i32 [[IV]], [[B]]

; CHECK-NEXT:    br i1 [[UNSIGNED_COND]], label [[INNER_BACKEDGE]], label [[SIDE_EXIT]]

; CHECK:       inner.backedge:

; CHECK-NEXT:    [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
@@ -493,7 +620,7 @@ define i32 @test_05a(i32 %a, i32* %bp) { 
; CHECK-NEXT:    ret i32 1

;

entry:

  %b = load i32, i32* %bp, !range !0

  %b = load i32, i32* %bp, !range !1

  br label %outer



outer:
@@ -503,11 +630,75 @@ outer: 


inner:

  %iv = phi i32 [%outer.iv, %outer], [%iv.next, %inner.backedge]

  %signed_cond = icmp ult i32 %iv, %b

  %signed_cond = icmp slt i32 %iv, %b

  br i1 %signed_cond, label %inner.1, label %side.exit



inner.1:

  %unsigned_cond = icmp slt i32 %iv, %b

  %unsigned_cond = icmp ult i32 %iv, %b

  br i1 %unsigned_cond, label %inner.backedge, label %side.exit



inner.backedge:

  %iv.next = add nuw nsw i32 %iv, 1

  %inner.loop.cond = call i1 @cond()

  br i1 %inner.loop.cond, label %inner, label %outer.backedge



outer.backedge:

  %outer.loop.cond = call i1 @cond()

  br i1 %outer.loop.cond, label %outer, label %exit



side.exit:

  ret i32 0



exit:

  ret i32 1

}



; Same as test_05c, but 2nd condition reversed.

; FIXME: Can remove 2nd check

define i32 @test_05d(i32 %a, i32* %bp) {

; CHECK-LABEL: @test_05d(

; CHECK-NEXT:  entry:

; CHECK-NEXT:    [[B:%.*]] = load i32, i32* [[BP:%.*]], align 4, !range [[RNG1]]

; CHECK-NEXT:    br label [[OUTER:%.*]]

; CHECK:       outer:

; CHECK-NEXT:    [[OUTER_IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT_LCSSA:%.*]], [[OUTER_BACKEDGE:%.*]] ]

; CHECK-NEXT:    br label [[INNER:%.*]]

; CHECK:       inner:

; CHECK-NEXT:    [[IV:%.*]] = phi i32 [ [[OUTER_IV]], [[OUTER]] ], [ [[IV_NEXT:%.*]], [[INNER_BACKEDGE:%.*]] ]

; CHECK-NEXT:    [[SIGNED_COND:%.*]] = icmp slt i32 [[IV]], [[B]]

; CHECK-NEXT:    br i1 [[SIGNED_COND]], label [[INNER_1:%.*]], label [[SIDE_EXIT:%.*]]

; CHECK:       inner.1:

; CHECK-NEXT:    [[UNSIGNED_COND:%.*]] = icmp ugt i32 [[B]], [[IV]]

; CHECK-NEXT:    br i1 [[UNSIGNED_COND]], label [[INNER_BACKEDGE]], label [[SIDE_EXIT]]

; CHECK:       inner.backedge:

; CHECK-NEXT:    [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1

; CHECK-NEXT:    [[INNER_LOOP_COND:%.*]] = call i1 @cond()

; CHECK-NEXT:    br i1 [[INNER_LOOP_COND]], label [[INNER]], label [[OUTER_BACKEDGE]]

; CHECK:       outer.backedge:

; CHECK-NEXT:    [[IV_NEXT_LCSSA]] = phi i32 [ [[IV_NEXT]], [[INNER_BACKEDGE]] ]

; CHECK-NEXT:    [[OUTER_LOOP_COND:%.*]] = call i1 @cond()

; CHECK-NEXT:    br i1 [[OUTER_LOOP_COND]], label [[OUTER]], label [[EXIT:%.*]]

; CHECK:       side.exit:

; CHECK-NEXT:    ret i32 0

; CHECK:       exit:

; CHECK-NEXT:    ret i32 1

;

entry:

  %b = load i32, i32* %bp, !range !1

  br label %outer



outer:

  %outer.iv = phi i32 [0, %entry], [%iv.next, %outer.backedge]

  br label %inner





inner:

  %iv = phi i32 [%outer.iv, %outer], [%iv.next, %inner.backedge]

  %signed_cond = icmp slt i32 %iv, %b

  br i1 %signed_cond, label %inner.1, label %side.exit



inner.1:

  %unsigned_cond = icmp ugt i32 %b, %iv

  br i1 %unsigned_cond, label %inner.backedge, label %side.exit



inner.backedge:
@@ -760,3 +951,4 @@ exit: 
}



!0 = !{i32 0, i32 2147483647}

!1 = !{i32 -2147483648, i32 0}