Unverified Commit 7874db75 authored by Roman Lebedev's avatar Roman Lebedev
Browse files

[NFC][Codegen] Add `x u% C1 == C2` with C1 u> C2 non-tautological tests

parent bcca123b

llvm/test/CodeGen/AArch64/urem-seteq-nonzero.ll

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+247 −0
Original line number Diff line number Diff line 
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py

; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s



define i1 @t32_3_1(i32 %X) nounwind {

; CHECK-LABEL: t32_3_1:

; CHECK:       // %bb.0:

; CHECK-NEXT:    mov w8, #43691

; CHECK-NEXT:    movk w8, #43690, lsl #16

; CHECK-NEXT:    umull x8, w0, w8

; CHECK-NEXT:    lsr x8, x8, #33

; CHECK-NEXT:    add w8, w8, w8, lsl #1

; CHECK-NEXT:    sub w8, w0, w8

; CHECK-NEXT:    cmp w8, #1 // =1

; CHECK-NEXT:    cset w0, eq

; CHECK-NEXT:    ret

  %urem = urem i32 %X, 3

  %cmp = icmp eq i32 %urem, 1

  ret i1 %cmp

}



define i1 @t32_3_2(i32 %X) nounwind {

; CHECK-LABEL: t32_3_2:

; CHECK:       // %bb.0:

; CHECK-NEXT:    mov w8, #43691

; CHECK-NEXT:    movk w8, #43690, lsl #16

; CHECK-NEXT:    umull x8, w0, w8

; CHECK-NEXT:    lsr x8, x8, #33

; CHECK-NEXT:    add w8, w8, w8, lsl #1

; CHECK-NEXT:    sub w8, w0, w8

; CHECK-NEXT:    cmp w8, #2 // =2

; CHECK-NEXT:    cset w0, eq

; CHECK-NEXT:    ret

  %urem = urem i32 %X, 3

  %cmp = icmp eq i32 %urem, 2

  ret i1 %cmp

}





define i1 @t32_5_1(i32 %X) nounwind {

; CHECK-LABEL: t32_5_1:

; CHECK:       // %bb.0:

; CHECK-NEXT:    mov w8, #52429

; CHECK-NEXT:    movk w8, #52428, lsl #16

; CHECK-NEXT:    umull x8, w0, w8

; CHECK-NEXT:    lsr x8, x8, #34

; CHECK-NEXT:    add w8, w8, w8, lsl #2

; CHECK-NEXT:    sub w8, w0, w8

; CHECK-NEXT:    cmp w8, #1 // =1

; CHECK-NEXT:    cset w0, eq

; CHECK-NEXT:    ret

  %urem = urem i32 %X, 5

  %cmp = icmp eq i32 %urem, 1

  ret i1 %cmp

}



define i1 @t32_5_2(i32 %X) nounwind {

; CHECK-LABEL: t32_5_2:

; CHECK:       // %bb.0:

; CHECK-NEXT:    mov w8, #52429

; CHECK-NEXT:    movk w8, #52428, lsl #16

; CHECK-NEXT:    umull x8, w0, w8

; CHECK-NEXT:    lsr x8, x8, #34

; CHECK-NEXT:    add w8, w8, w8, lsl #2

; CHECK-NEXT:    sub w8, w0, w8

; CHECK-NEXT:    cmp w8, #2 // =2

; CHECK-NEXT:    cset w0, eq

; CHECK-NEXT:    ret

  %urem = urem i32 %X, 5

  %cmp = icmp eq i32 %urem, 2

  ret i1 %cmp

}



define i1 @t32_5_3(i32 %X) nounwind {

; CHECK-LABEL: t32_5_3:

; CHECK:       // %bb.0:

; CHECK-NEXT:    mov w8, #52429

; CHECK-NEXT:    movk w8, #52428, lsl #16

; CHECK-NEXT:    umull x8, w0, w8

; CHECK-NEXT:    lsr x8, x8, #34

; CHECK-NEXT:    add w8, w8, w8, lsl #2

; CHECK-NEXT:    sub w8, w0, w8

; CHECK-NEXT:    cmp w8, #3 // =3

; CHECK-NEXT:    cset w0, eq

; CHECK-NEXT:    ret

  %urem = urem i32 %X, 5

  %cmp = icmp eq i32 %urem, 3

  ret i1 %cmp

}



define i1 @t32_5_4(i32 %X) nounwind {

; CHECK-LABEL: t32_5_4:

; CHECK:       // %bb.0:

; CHECK-NEXT:    mov w8, #52429

; CHECK-NEXT:    movk w8, #52428, lsl #16

; CHECK-NEXT:    umull x8, w0, w8

; CHECK-NEXT:    lsr x8, x8, #34

; CHECK-NEXT:    add w8, w8, w8, lsl #2

; CHECK-NEXT:    sub w8, w0, w8

; CHECK-NEXT:    cmp w8, #4 // =4

; CHECK-NEXT:    cset w0, eq

; CHECK-NEXT:    ret

  %urem = urem i32 %X, 5

  %cmp = icmp eq i32 %urem, 4

  ret i1 %cmp

}





define i1 @t32_6_1(i32 %X) nounwind {

; CHECK-LABEL: t32_6_1:

; CHECK:       // %bb.0:

; CHECK-NEXT:    mov w8, #43691

; CHECK-NEXT:    movk w8, #43690, lsl #16

; CHECK-NEXT:    umull x8, w0, w8

; CHECK-NEXT:    lsr x8, x8, #34

; CHECK-NEXT:    mov w9, #6

; CHECK-NEXT:    msub w8, w8, w9, w0

; CHECK-NEXT:    cmp w8, #1 // =1

; CHECK-NEXT:    cset w0, eq

; CHECK-NEXT:    ret

  %urem = urem i32 %X, 6

  %cmp = icmp eq i32 %urem, 1

  ret i1 %cmp

}



define i1 @t32_6_2(i32 %X) nounwind {

; CHECK-LABEL: t32_6_2:

; CHECK:       // %bb.0:

; CHECK-NEXT:    mov w8, #43691

; CHECK-NEXT:    movk w8, #43690, lsl #16

; CHECK-NEXT:    umull x8, w0, w8

; CHECK-NEXT:    lsr x8, x8, #34

; CHECK-NEXT:    mov w9, #6

; CHECK-NEXT:    msub w8, w8, w9, w0

; CHECK-NEXT:    cmp w8, #2 // =2

; CHECK-NEXT:    cset w0, eq

; CHECK-NEXT:    ret

  %urem = urem i32 %X, 6

  %cmp = icmp eq i32 %urem, 2

  ret i1 %cmp

}



define i1 @t32_6_3(i32 %X) nounwind {

; CHECK-LABEL: t32_6_3:

; CHECK:       // %bb.0:

; CHECK-NEXT:    mov w8, #43691

; CHECK-NEXT:    movk w8, #43690, lsl #16

; CHECK-NEXT:    umull x8, w0, w8

; CHECK-NEXT:    lsr x8, x8, #34

; CHECK-NEXT:    mov w9, #6

; CHECK-NEXT:    msub w8, w8, w9, w0

; CHECK-NEXT:    cmp w8, #3 // =3

; CHECK-NEXT:    cset w0, eq

; CHECK-NEXT:    ret

  %urem = urem i32 %X, 6

  %cmp = icmp eq i32 %urem, 3

  ret i1 %cmp

}



define i1 @t32_6_4(i32 %X) nounwind {

; CHECK-LABEL: t32_6_4:

; CHECK:       // %bb.0:

; CHECK-NEXT:    mov w8, #43691

; CHECK-NEXT:    movk w8, #43690, lsl #16

; CHECK-NEXT:    umull x8, w0, w8

; CHECK-NEXT:    lsr x8, x8, #34

; CHECK-NEXT:    mov w9, #6

; CHECK-NEXT:    msub w8, w8, w9, w0

; CHECK-NEXT:    cmp w8, #4 // =4

; CHECK-NEXT:    cset w0, eq

; CHECK-NEXT:    ret

  %urem = urem i32 %X, 6

  %cmp = icmp eq i32 %urem, 4

  ret i1 %cmp

}



define i1 @t32_6_5(i32 %X) nounwind {

; CHECK-LABEL: t32_6_5:

; CHECK:       // %bb.0:

; CHECK-NEXT:    mov w8, #43691

; CHECK-NEXT:    movk w8, #43690, lsl #16

; CHECK-NEXT:    umull x8, w0, w8

; CHECK-NEXT:    lsr x8, x8, #34

; CHECK-NEXT:    mov w9, #6

; CHECK-NEXT:    msub w8, w8, w9, w0

; CHECK-NEXT:    cmp w8, #5 // =5

; CHECK-NEXT:    cset w0, eq

; CHECK-NEXT:    ret

  %urem = urem i32 %X, 6

  %cmp = icmp eq i32 %urem, 5

  ret i1 %cmp

}



;-------------------------------------------------------------------------------

; Other widths.



define i1 @t16_3_2(i16 %X) nounwind {

; CHECK-LABEL: t16_3_2:

; CHECK:       // %bb.0:

; CHECK-NEXT:    mov w9, #43691

; CHECK-NEXT:    and w8, w0, #0xffff

; CHECK-NEXT:    movk w9, #43690, lsl #16

; CHECK-NEXT:    umull x9, w8, w9

; CHECK-NEXT:    lsr x9, x9, #33

; CHECK-NEXT:    add w9, w9, w9, lsl #1

; CHECK-NEXT:    sub w8, w8, w9

; CHECK-NEXT:    cmp w8, #2 // =2

; CHECK-NEXT:    cset w0, eq

; CHECK-NEXT:    ret

  %urem = urem i16 %X, 3

  %cmp = icmp eq i16 %urem, 2

  ret i1 %cmp

}



define i1 @t8_3_2(i8 %X) nounwind {

; CHECK-LABEL: t8_3_2:

; CHECK:       // %bb.0:

; CHECK-NEXT:    mov w9, #43691

; CHECK-NEXT:    and w8, w0, #0xff

; CHECK-NEXT:    movk w9, #43690, lsl #16

; CHECK-NEXT:    umull x9, w8, w9

; CHECK-NEXT:    lsr x9, x9, #33

; CHECK-NEXT:    add w9, w9, w9, lsl #1

; CHECK-NEXT:    sub w8, w8, w9

; CHECK-NEXT:    cmp w8, #2 // =2

; CHECK-NEXT:    cset w0, eq

; CHECK-NEXT:    ret

  %urem = urem i8 %X, 3

  %cmp = icmp eq i8 %urem, 2

  ret i1 %cmp

}



define i1 @t64_3_2(i64 %X) nounwind {

; CHECK-LABEL: t64_3_2:

; CHECK:       // %bb.0:

; CHECK-NEXT:    mov x8, #-6148914691236517206

; CHECK-NEXT:    movk x8, #43691

; CHECK-NEXT:    umulh x8, x0, x8

; CHECK-NEXT:    lsr x8, x8, #1

; CHECK-NEXT:    add x8, x8, x8, lsl #1

; CHECK-NEXT:    sub x8, x0, x8

; CHECK-NEXT:    cmp x8, #2 // =2

; CHECK-NEXT:    cset w0, eq

; CHECK-NEXT:    ret

  %urem = urem i64 %X, 3

  %cmp = icmp eq i64 %urem, 2

  ret i1 %cmp

}

llvm/test/CodeGen/AArch64/urem-seteq-vec-nonzero.ll

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Original line number Diff line number Diff line 
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py

; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s



define <4 x i1> @t32_3(<4 x i32> %X) nounwind {

; CHECK-LABEL: t32_3:

; CHECK:       // %bb.0:

; CHECK-NEXT:    mov w8, #43691

; CHECK-NEXT:    movk w8, #43690, lsl #16

; CHECK-NEXT:    adrp x9, .LCPI0_0

; CHECK-NEXT:    dup v1.4s, w8

; CHECK-NEXT:    ldr q2, [x9, :lo12:.LCPI0_0]

; CHECK-NEXT:    umull2 v3.2d, v0.4s, v1.4s

; CHECK-NEXT:    umull v1.2d, v0.2s, v1.2s

; CHECK-NEXT:    uzp2 v1.4s, v1.4s, v3.4s

; CHECK-NEXT:    ushr v1.4s, v1.4s, #1

; CHECK-NEXT:    movi v3.4s, #3

; CHECK-NEXT:    mls v0.4s, v1.4s, v3.4s

; CHECK-NEXT:    cmeq v0.4s, v0.4s, v2.4s

; CHECK-NEXT:    xtn v0.4h, v0.4s

; CHECK-NEXT:    ret

  %urem = urem <4 x i32> %X, <i32 3, i32 3, i32 3, i32 3>

  %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 1, i32 2, i32 2>

  ret <4 x i1> %cmp

}



define <4 x i1> @t32_5(<4 x i32> %X) nounwind {

; CHECK-LABEL: t32_5:

; CHECK:       // %bb.0:

; CHECK-NEXT:    mov w8, #52429

; CHECK-NEXT:    movk w8, #52428, lsl #16

; CHECK-NEXT:    adrp x9, .LCPI1_0

; CHECK-NEXT:    dup v1.4s, w8

; CHECK-NEXT:    ldr q2, [x9, :lo12:.LCPI1_0]

; CHECK-NEXT:    umull2 v3.2d, v0.4s, v1.4s

; CHECK-NEXT:    umull v1.2d, v0.2s, v1.2s

; CHECK-NEXT:    uzp2 v1.4s, v1.4s, v3.4s

; CHECK-NEXT:    ushr v1.4s, v1.4s, #2

; CHECK-NEXT:    movi v3.4s, #5

; CHECK-NEXT:    mls v0.4s, v1.4s, v3.4s

; CHECK-NEXT:    cmeq v0.4s, v0.4s, v2.4s

; CHECK-NEXT:    xtn v0.4h, v0.4s

; CHECK-NEXT:    ret

  %urem = urem <4 x i32> %X, <i32 5, i32 5, i32 5, i32 5>

  %cmp = icmp eq <4 x i32> %urem, <i32 1, i32 2, i32 3, i32 4>

  ret <4 x i1> %cmp

}



define <4 x i1> @t32_6_part0(<4 x i32> %X) nounwind {

; CHECK-LABEL: t32_6_part0:

; CHECK:       // %bb.0:

; CHECK-NEXT:    mov w8, #43691

; CHECK-NEXT:    movk w8, #43690, lsl #16

; CHECK-NEXT:    adrp x9, .LCPI2_0

; CHECK-NEXT:    dup v1.4s, w8

; CHECK-NEXT:    ldr q2, [x9, :lo12:.LCPI2_0]

; CHECK-NEXT:    umull2 v3.2d, v0.4s, v1.4s

; CHECK-NEXT:    umull v1.2d, v0.2s, v1.2s

; CHECK-NEXT:    uzp2 v1.4s, v1.4s, v3.4s

; CHECK-NEXT:    ushr v1.4s, v1.4s, #2

; CHECK-NEXT:    movi v3.4s, #6

; CHECK-NEXT:    mls v0.4s, v1.4s, v3.4s

; CHECK-NEXT:    cmeq v0.4s, v0.4s, v2.4s

; CHECK-NEXT:    xtn v0.4h, v0.4s

; CHECK-NEXT:    ret

  %urem = urem <4 x i32> %X, <i32 6, i32 6, i32 6, i32 6>

  %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 1, i32 2, i32 3>

  ret <4 x i1> %cmp

}



define <4 x i1> @t32_6_part1(<4 x i32> %X) nounwind {

; CHECK-LABEL: t32_6_part1:

; CHECK:       // %bb.0:

; CHECK-NEXT:    mov w8, #43691

; CHECK-NEXT:    movk w8, #43690, lsl #16

; CHECK-NEXT:    adrp x9, .LCPI3_0

; CHECK-NEXT:    dup v1.4s, w8

; CHECK-NEXT:    ldr q2, [x9, :lo12:.LCPI3_0]

; CHECK-NEXT:    umull2 v3.2d, v0.4s, v1.4s

; CHECK-NEXT:    umull v1.2d, v0.2s, v1.2s

; CHECK-NEXT:    uzp2 v1.4s, v1.4s, v3.4s

; CHECK-NEXT:    ushr v1.4s, v1.4s, #2

; CHECK-NEXT:    movi v3.4s, #6

; CHECK-NEXT:    mls v0.4s, v1.4s, v3.4s

; CHECK-NEXT:    cmeq v0.4s, v0.4s, v2.4s

; CHECK-NEXT:    xtn v0.4h, v0.4s

; CHECK-NEXT:    ret

  %urem = urem <4 x i32> %X, <i32 6, i32 6, i32 6, i32 6>

  %cmp = icmp eq <4 x i32> %urem, <i32 4, i32 5, i32 0, i32 0>

  ret <4 x i1> %cmp

}



define <4 x i1> @t32_tautological(<4 x i32> %X) nounwind {

; CHECK-LABEL: t32_tautological:

; CHECK:       // %bb.0:

; CHECK-NEXT:    adrp x8, .LCPI4_0

; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI4_0]

; CHECK-NEXT:    adrp x8, .LCPI4_1

; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI4_1]

; CHECK-NEXT:    adrp x8, .LCPI4_2

; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI4_2]

; CHECK-NEXT:    adrp x8, .LCPI4_3

; CHECK-NEXT:    ldr q4, [x8, :lo12:.LCPI4_3]

; CHECK-NEXT:    adrp x8, .LCPI4_4

; CHECK-NEXT:    umull2 v5.2d, v0.4s, v1.4s

; CHECK-NEXT:    umull v1.2d, v0.2s, v1.2s

; CHECK-NEXT:    neg v2.4s, v2.4s

; CHECK-NEXT:    uzp2 v1.4s, v1.4s, v5.4s

; CHECK-NEXT:    ldr q5, [x8, :lo12:.LCPI4_4]

; CHECK-NEXT:    ushl v1.4s, v1.4s, v2.4s

; CHECK-NEXT:    bsl v3.16b, v0.16b, v1.16b

; CHECK-NEXT:    mls v0.4s, v3.4s, v4.4s

; CHECK-NEXT:    cmeq v0.4s, v0.4s, v5.4s

; CHECK-NEXT:    xtn v0.4h, v0.4s

; CHECK-NEXT:    ret

  %urem = urem <4 x i32> %X, <i32 1, i32 1, i32 2, i32 3>

  %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 1, i32 2, i32 2>

  ret <4 x i1> %cmp

}

llvm/test/CodeGen/X86/urem-seteq-nonzero.ll

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+434 −0
Original line number Diff line number Diff line 
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py

; RUN: llc -mtriple=i686-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,X86

; RUN: llc -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,X64



define i1 @t32_3_1(i32 %X) nounwind {

; X86-LABEL: t32_3_1:

; X86:       # %bb.0:

; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx

; X86-NEXT:    movl $-1431655765, %edx # imm = 0xAAAAAAAB

; X86-NEXT:    movl %ecx, %eax

; X86-NEXT:    mull %edx

; X86-NEXT:    shrl %edx

; X86-NEXT:    leal (%edx,%edx,2), %eax

; X86-NEXT:    subl %eax, %ecx

; X86-NEXT:    cmpl $1, %ecx

; X86-NEXT:    sete %al

; X86-NEXT:    retl

;

; X64-LABEL: t32_3_1:

; X64:       # %bb.0:

; X64-NEXT:    movl %edi, %eax

; X64-NEXT:    movl $2863311531, %ecx # imm = 0xAAAAAAAB

; X64-NEXT:    imulq %rax, %rcx

; X64-NEXT:    shrq $33, %rcx

; X64-NEXT:    leal (%rcx,%rcx,2), %eax

; X64-NEXT:    subl %eax, %edi

; X64-NEXT:    cmpl $1, %edi

; X64-NEXT:    sete %al

; X64-NEXT:    retq

  %urem = urem i32 %X, 3

  %cmp = icmp eq i32 %urem, 1

  ret i1 %cmp

}



define i1 @t32_3_2(i32 %X) nounwind {

; X86-LABEL: t32_3_2:

; X86:       # %bb.0:

; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx

; X86-NEXT:    movl $-1431655765, %edx # imm = 0xAAAAAAAB

; X86-NEXT:    movl %ecx, %eax

; X86-NEXT:    mull %edx

; X86-NEXT:    shrl %edx

; X86-NEXT:    leal (%edx,%edx,2), %eax

; X86-NEXT:    subl %eax, %ecx

; X86-NEXT:    cmpl $2, %ecx

; X86-NEXT:    sete %al

; X86-NEXT:    retl

;

; X64-LABEL: t32_3_2:

; X64:       # %bb.0:

; X64-NEXT:    movl %edi, %eax

; X64-NEXT:    movl $2863311531, %ecx # imm = 0xAAAAAAAB

; X64-NEXT:    imulq %rax, %rcx

; X64-NEXT:    shrq $33, %rcx

; X64-NEXT:    leal (%rcx,%rcx,2), %eax

; X64-NEXT:    subl %eax, %edi

; X64-NEXT:    cmpl $2, %edi

; X64-NEXT:    sete %al

; X64-NEXT:    retq

  %urem = urem i32 %X, 3

  %cmp = icmp eq i32 %urem, 2

  ret i1 %cmp

}





define i1 @t32_5_1(i32 %X) nounwind {

; X86-LABEL: t32_5_1:

; X86:       # %bb.0:

; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx

; X86-NEXT:    movl $-858993459, %edx # imm = 0xCCCCCCCD

; X86-NEXT:    movl %ecx, %eax

; X86-NEXT:    mull %edx

; X86-NEXT:    shrl $2, %edx

; X86-NEXT:    leal (%edx,%edx,4), %eax

; X86-NEXT:    subl %eax, %ecx

; X86-NEXT:    cmpl $1, %ecx

; X86-NEXT:    sete %al

; X86-NEXT:    retl

;

; X64-LABEL: t32_5_1:

; X64:       # %bb.0:

; X64-NEXT:    movl %edi, %eax

; X64-NEXT:    movl $3435973837, %ecx # imm = 0xCCCCCCCD

; X64-NEXT:    imulq %rax, %rcx

; X64-NEXT:    shrq $34, %rcx

; X64-NEXT:    leal (%rcx,%rcx,4), %eax

; X64-NEXT:    subl %eax, %edi

; X64-NEXT:    cmpl $1, %edi

; X64-NEXT:    sete %al

; X64-NEXT:    retq

  %urem = urem i32 %X, 5

  %cmp = icmp eq i32 %urem, 1

  ret i1 %cmp

}



define i1 @t32_5_2(i32 %X) nounwind {

; X86-LABEL: t32_5_2:

; X86:       # %bb.0:

; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx

; X86-NEXT:    movl $-858993459, %edx # imm = 0xCCCCCCCD

; X86-NEXT:    movl %ecx, %eax

; X86-NEXT:    mull %edx

; X86-NEXT:    shrl $2, %edx

; X86-NEXT:    leal (%edx,%edx,4), %eax

; X86-NEXT:    subl %eax, %ecx

; X86-NEXT:    cmpl $2, %ecx

; X86-NEXT:    sete %al

; X86-NEXT:    retl

;

; X64-LABEL: t32_5_2:

; X64:       # %bb.0:

; X64-NEXT:    movl %edi, %eax

; X64-NEXT:    movl $3435973837, %ecx # imm = 0xCCCCCCCD

; X64-NEXT:    imulq %rax, %rcx

; X64-NEXT:    shrq $34, %rcx

; X64-NEXT:    leal (%rcx,%rcx,4), %eax

; X64-NEXT:    subl %eax, %edi

; X64-NEXT:    cmpl $2, %edi

; X64-NEXT:    sete %al

; X64-NEXT:    retq

  %urem = urem i32 %X, 5

  %cmp = icmp eq i32 %urem, 2

  ret i1 %cmp

}



define i1 @t32_5_3(i32 %X) nounwind {

; X86-LABEL: t32_5_3:

; X86:       # %bb.0:

; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx

; X86-NEXT:    movl $-858993459, %edx # imm = 0xCCCCCCCD

; X86-NEXT:    movl %ecx, %eax

; X86-NEXT:    mull %edx

; X86-NEXT:    shrl $2, %edx

; X86-NEXT:    leal (%edx,%edx,4), %eax

; X86-NEXT:    subl %eax, %ecx

; X86-NEXT:    cmpl $3, %ecx

; X86-NEXT:    sete %al

; X86-NEXT:    retl

;

; X64-LABEL: t32_5_3:

; X64:       # %bb.0:

; X64-NEXT:    movl %edi, %eax

; X64-NEXT:    movl $3435973837, %ecx # imm = 0xCCCCCCCD

; X64-NEXT:    imulq %rax, %rcx

; X64-NEXT:    shrq $34, %rcx

; X64-NEXT:    leal (%rcx,%rcx,4), %eax

; X64-NEXT:    subl %eax, %edi

; X64-NEXT:    cmpl $3, %edi

; X64-NEXT:    sete %al

; X64-NEXT:    retq

  %urem = urem i32 %X, 5

  %cmp = icmp eq i32 %urem, 3

  ret i1 %cmp

}



define i1 @t32_5_4(i32 %X) nounwind {

; X86-LABEL: t32_5_4:

; X86:       # %bb.0:

; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx

; X86-NEXT:    movl $-858993459, %edx # imm = 0xCCCCCCCD

; X86-NEXT:    movl %ecx, %eax

; X86-NEXT:    mull %edx

; X86-NEXT:    shrl $2, %edx

; X86-NEXT:    leal (%edx,%edx,4), %eax

; X86-NEXT:    subl %eax, %ecx

; X86-NEXT:    cmpl $4, %ecx

; X86-NEXT:    sete %al

; X86-NEXT:    retl

;

; X64-LABEL: t32_5_4:

; X64:       # %bb.0:

; X64-NEXT:    movl %edi, %eax

; X64-NEXT:    movl $3435973837, %ecx # imm = 0xCCCCCCCD

; X64-NEXT:    imulq %rax, %rcx

; X64-NEXT:    shrq $34, %rcx

; X64-NEXT:    leal (%rcx,%rcx,4), %eax

; X64-NEXT:    subl %eax, %edi

; X64-NEXT:    cmpl $4, %edi

; X64-NEXT:    sete %al

; X64-NEXT:    retq

  %urem = urem i32 %X, 5

  %cmp = icmp eq i32 %urem, 4

  ret i1 %cmp

}





define i1 @t32_6_1(i32 %X) nounwind {

; X86-LABEL: t32_6_1:

; X86:       # %bb.0:

; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx

; X86-NEXT:    movl $-1431655765, %edx # imm = 0xAAAAAAAB

; X86-NEXT:    movl %ecx, %eax

; X86-NEXT:    mull %edx

; X86-NEXT:    shrl %edx

; X86-NEXT:    andl $-2, %edx

; X86-NEXT:    leal (%edx,%edx,2), %eax

; X86-NEXT:    subl %eax, %ecx

; X86-NEXT:    cmpl $1, %ecx

; X86-NEXT:    sete %al

; X86-NEXT:    retl

;

; X64-LABEL: t32_6_1:

; X64:       # %bb.0:

; X64-NEXT:    movl %edi, %eax

; X64-NEXT:    movl $2863311531, %ecx # imm = 0xAAAAAAAB

; X64-NEXT:    imulq %rax, %rcx

; X64-NEXT:    shrq $34, %rcx

; X64-NEXT:    addl %ecx, %ecx

; X64-NEXT:    leal (%rcx,%rcx,2), %eax

; X64-NEXT:    subl %eax, %edi

; X64-NEXT:    cmpl $1, %edi

; X64-NEXT:    sete %al

; X64-NEXT:    retq

  %urem = urem i32 %X, 6

  %cmp = icmp eq i32 %urem, 1

  ret i1 %cmp

}



define i1 @t32_6_2(i32 %X) nounwind {

; X86-LABEL: t32_6_2:

; X86:       # %bb.0:

; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx

; X86-NEXT:    movl $-1431655765, %edx # imm = 0xAAAAAAAB

; X86-NEXT:    movl %ecx, %eax

; X86-NEXT:    mull %edx

; X86-NEXT:    shrl %edx

; X86-NEXT:    andl $-2, %edx

; X86-NEXT:    leal (%edx,%edx,2), %eax

; X86-NEXT:    subl %eax, %ecx

; X86-NEXT:    cmpl $2, %ecx

; X86-NEXT:    sete %al

; X86-NEXT:    retl

;

; X64-LABEL: t32_6_2:

; X64:       # %bb.0:

; X64-NEXT:    movl %edi, %eax

; X64-NEXT:    movl $2863311531, %ecx # imm = 0xAAAAAAAB

; X64-NEXT:    imulq %rax, %rcx

; X64-NEXT:    shrq $34, %rcx

; X64-NEXT:    addl %ecx, %ecx

; X64-NEXT:    leal (%rcx,%rcx,2), %eax

; X64-NEXT:    subl %eax, %edi

; X64-NEXT:    cmpl $2, %edi

; X64-NEXT:    sete %al

; X64-NEXT:    retq

  %urem = urem i32 %X, 6

  %cmp = icmp eq i32 %urem, 2

  ret i1 %cmp

}



define i1 @t32_6_3(i32 %X) nounwind {

; X86-LABEL: t32_6_3:

; X86:       # %bb.0:

; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx

; X86-NEXT:    movl $-1431655765, %edx # imm = 0xAAAAAAAB

; X86-NEXT:    movl %ecx, %eax

; X86-NEXT:    mull %edx

; X86-NEXT:    shrl %edx

; X86-NEXT:    andl $-2, %edx

; X86-NEXT:    leal (%edx,%edx,2), %eax

; X86-NEXT:    subl %eax, %ecx

; X86-NEXT:    cmpl $3, %ecx

; X86-NEXT:    sete %al

; X86-NEXT:    retl

;

; X64-LABEL: t32_6_3:

; X64:       # %bb.0:

; X64-NEXT:    movl %edi, %eax

; X64-NEXT:    movl $2863311531, %ecx # imm = 0xAAAAAAAB

; X64-NEXT:    imulq %rax, %rcx

; X64-NEXT:    shrq $34, %rcx

; X64-NEXT:    addl %ecx, %ecx

; X64-NEXT:    leal (%rcx,%rcx,2), %eax

; X64-NEXT:    subl %eax, %edi

; X64-NEXT:    cmpl $3, %edi

; X64-NEXT:    sete %al

; X64-NEXT:    retq

  %urem = urem i32 %X, 6

  %cmp = icmp eq i32 %urem, 3

  ret i1 %cmp

}



define i1 @t32_6_4(i32 %X) nounwind {

; X86-LABEL: t32_6_4:

; X86:       # %bb.0:

; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx

; X86-NEXT:    movl $-1431655765, %edx # imm = 0xAAAAAAAB

; X86-NEXT:    movl %ecx, %eax

; X86-NEXT:    mull %edx

; X86-NEXT:    shrl %edx

; X86-NEXT:    andl $-2, %edx

; X86-NEXT:    leal (%edx,%edx,2), %eax

; X86-NEXT:    subl %eax, %ecx

; X86-NEXT:    cmpl $4, %ecx

; X86-NEXT:    sete %al

; X86-NEXT:    retl

;

; X64-LABEL: t32_6_4:

; X64:       # %bb.0:

; X64-NEXT:    movl %edi, %eax

; X64-NEXT:    movl $2863311531, %ecx # imm = 0xAAAAAAAB

; X64-NEXT:    imulq %rax, %rcx

; X64-NEXT:    shrq $34, %rcx

; X64-NEXT:    addl %ecx, %ecx

; X64-NEXT:    leal (%rcx,%rcx,2), %eax

; X64-NEXT:    subl %eax, %edi

; X64-NEXT:    cmpl $4, %edi

; X64-NEXT:    sete %al

; X64-NEXT:    retq

  %urem = urem i32 %X, 6

  %cmp = icmp eq i32 %urem, 4

  ret i1 %cmp

}



define i1 @t32_6_5(i32 %X) nounwind {

; X86-LABEL: t32_6_5:

; X86:       # %bb.0:

; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx

; X86-NEXT:    movl $-1431655765, %edx # imm = 0xAAAAAAAB

; X86-NEXT:    movl %ecx, %eax

; X86-NEXT:    mull %edx

; X86-NEXT:    shrl %edx

; X86-NEXT:    andl $-2, %edx

; X86-NEXT:    leal (%edx,%edx,2), %eax

; X86-NEXT:    subl %eax, %ecx

; X86-NEXT:    cmpl $5, %ecx

; X86-NEXT:    sete %al

; X86-NEXT:    retl

;

; X64-LABEL: t32_6_5:

; X64:       # %bb.0:

; X64-NEXT:    movl %edi, %eax

; X64-NEXT:    movl $2863311531, %ecx # imm = 0xAAAAAAAB

; X64-NEXT:    imulq %rax, %rcx

; X64-NEXT:    shrq $34, %rcx

; X64-NEXT:    addl %ecx, %ecx

; X64-NEXT:    leal (%rcx,%rcx,2), %eax

; X64-NEXT:    subl %eax, %edi

; X64-NEXT:    cmpl $5, %edi

; X64-NEXT:    sete %al

; X64-NEXT:    retq

  %urem = urem i32 %X, 6

  %cmp = icmp eq i32 %urem, 5

  ret i1 %cmp

}



;-------------------------------------------------------------------------------

; Other widths.



define i1 @t16_3_2(i16 %X) nounwind {

; X86-LABEL: t16_3_2:

; X86:       # %bb.0:

; X86-NEXT:    movzwl {{[0-9]+}}(%esp), %eax

; X86-NEXT:    imull $43691, %eax, %ecx # imm = 0xAAAB

; X86-NEXT:    shrl $17, %ecx

; X86-NEXT:    leal (%ecx,%ecx,2), %ecx

; X86-NEXT:    subl %ecx, %eax

; X86-NEXT:    cmpw $2, %ax

; X86-NEXT:    sete %al

; X86-NEXT:    retl

;

; X64-LABEL: t16_3_2:

; X64:       # %bb.0:

; X64-NEXT:    movzwl %di, %eax

; X64-NEXT:    imull $43691, %eax, %eax # imm = 0xAAAB

; X64-NEXT:    shrl $17, %eax

; X64-NEXT:    leal (%rax,%rax,2), %eax

; X64-NEXT:    subl %eax, %edi

; X64-NEXT:    cmpw $2, %di

; X64-NEXT:    sete %al

; X64-NEXT:    retq

  %urem = urem i16 %X, 3

  %cmp = icmp eq i16 %urem, 2

  ret i1 %cmp

}



define i1 @t8_3_2(i8 %X) nounwind {

; X86-LABEL: t8_3_2:

; X86:       # %bb.0:

; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax

; X86-NEXT:    imull $171, %eax, %ecx

; X86-NEXT:    shrl $9, %ecx

; X86-NEXT:    leal (%ecx,%ecx,2), %ecx

; X86-NEXT:    subb %cl, %al

; X86-NEXT:    cmpb $2, %al

; X86-NEXT:    sete %al

; X86-NEXT:    retl

;

; X64-LABEL: t8_3_2:

; X64:       # %bb.0:

; X64-NEXT:    movzbl %dil, %eax

; X64-NEXT:    imull $171, %eax, %ecx

; X64-NEXT:    shrl $9, %ecx

; X64-NEXT:    leal (%rcx,%rcx,2), %ecx

; X64-NEXT:    subb %cl, %al

; X64-NEXT:    cmpb $2, %al

; X64-NEXT:    sete %al

; X64-NEXT:    retq

  %urem = urem i8 %X, 3

  %cmp = icmp eq i8 %urem, 2

  ret i1 %cmp

}



define i1 @t64_3_2(i64 %X) nounwind {

; X86-LABEL: t64_3_2:

; X86:       # %bb.0:

; X86-NEXT:    subl $12, %esp

; X86-NEXT:    pushl $0

; X86-NEXT:    pushl $3

; X86-NEXT:    pushl {{[0-9]+}}(%esp)

; X86-NEXT:    pushl {{[0-9]+}}(%esp)

; X86-NEXT:    calll __umoddi3

; X86-NEXT:    addl $16, %esp

; X86-NEXT:    xorl $2, %eax

; X86-NEXT:    orl %edx, %eax

; X86-NEXT:    sete %al

; X86-NEXT:    addl $12, %esp

; X86-NEXT:    retl

;

; X64-LABEL: t64_3_2:

; X64:       # %bb.0:

; X64-NEXT:    movabsq $-6148914691236517205, %rcx # imm = 0xAAAAAAAAAAAAAAAB

; X64-NEXT:    movq %rdi, %rax

; X64-NEXT:    mulq %rcx

; X64-NEXT:    shrq %rdx

; X64-NEXT:    leaq (%rdx,%rdx,2), %rax

; X64-NEXT:    subq %rax, %rdi

; X64-NEXT:    cmpq $2, %rdi

; X64-NEXT:    sete %al

; X64-NEXT:    retq

  %urem = urem i64 %X, 3

  %cmp = icmp eq i64 %urem, 2

  ret i1 %cmp

}

llvm/test/CodeGen/X86/urem-seteq-vec-nonzero.ll

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