Commit 7801d796 authored by David Green's avatar David Green
Browse files

[DAG] Add tests for select_cc and setcc with constant patterns.

parent 9b015383

llvm/test/CodeGen/AArch64/select-constant-xor.ll

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Original line number Diff line number Diff line 
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py

; RUN: llc -mtriple=aarch64-none-none-eabi %s -o - | FileCheck %s



define i32 @xori64i32(i64 %a) {

; CHECK-LABEL: xori64i32:

; CHECK:       // %bb.0:

; CHECK-NEXT:    asr x8, x0, #63

; CHECK-NEXT:    eor w0, w8, #0x7fffffff

; CHECK-NEXT:    ret

  %shr4 = ashr i64 %a, 63

  %conv5 = trunc i64 %shr4 to i32

  %xor = xor i32 %conv5, 2147483647

  ret i32 %xor

}



define i64 @selecti64i64(i64 %a) {

; CHECK-LABEL: selecti64i64:

; CHECK:       // %bb.0:

; CHECK-NEXT:    cmp x0, #0

; CHECK-NEXT:    mov w8, #2147483647

; CHECK-NEXT:    cinv x0, x8, lt

; CHECK-NEXT:    ret

  %c = icmp sgt i64 %a, -1

  %s = select i1 %c, i64 2147483647, i64 -2147483648

  ret i64 %s

}



define i32 @selecti64i32(i64 %a) {

; CHECK-LABEL: selecti64i32:

; CHECK:       // %bb.0:

; CHECK-NEXT:    cmp x0, #0

; CHECK-NEXT:    mov w8, #2147483647

; CHECK-NEXT:    cinv w0, w8, lt

; CHECK-NEXT:    ret

  %c = icmp sgt i64 %a, -1

  %s = select i1 %c, i32 2147483647, i32 -2147483648

  ret i32 %s

}



define i64 @selecti32i64(i32 %a) {

; CHECK-LABEL: selecti32i64:

; CHECK:       // %bb.0:

; CHECK-NEXT:    cmp w0, #0

; CHECK-NEXT:    mov w8, #2147483647

; CHECK-NEXT:    cinv x0, x8, lt

; CHECK-NEXT:    ret

  %c = icmp sgt i32 %a, -1

  %s = select i1 %c, i64 2147483647, i64 -2147483648

  ret i64 %s

}







define i8 @xori32i8(i32 %a) {

; CHECK-LABEL: xori32i8:

; CHECK:       // %bb.0:

; CHECK-NEXT:    mov w8, #84

; CHECK-NEXT:    eor w0, w8, w0, asr #31

; CHECK-NEXT:    ret

  %shr4 = ashr i32 %a, 31

  %conv5 = trunc i32 %shr4 to i8

  %xor = xor i8 %conv5, 84

  ret i8 %xor

}



define i32 @selecti32i32(i32 %a) {

; CHECK-LABEL: selecti32i32:

; CHECK:       // %bb.0:

; CHECK-NEXT:    cmp w0, #0

; CHECK-NEXT:    mov w8, #84

; CHECK-NEXT:    cinv w0, w8, lt

; CHECK-NEXT:    ret

  %c = icmp sgt i32 %a, -1

  %s = select i1 %c, i32 84, i32 -85

  ret i32 %s

}



define i8 @selecti32i8(i32 %a) {

; CHECK-LABEL: selecti32i8:

; CHECK:       // %bb.0:

; CHECK-NEXT:    cmp w0, #0

; CHECK-NEXT:    mov w8, #84

; CHECK-NEXT:    cinv w0, w8, lt

; CHECK-NEXT:    ret

  %c = icmp sgt i32 %a, -1

  %s = select i1 %c, i8 84, i8 -85

  ret i8 %s

}



define i32 @selecti8i32(i8 %a) {

; CHECK-LABEL: selecti8i32:

; CHECK:       // %bb.0:

; CHECK-NEXT:    sxtb w8, w0

; CHECK-NEXT:    cmp w8, #0

; CHECK-NEXT:    mov w8, #84

; CHECK-NEXT:    cinv w0, w8, lt

; CHECK-NEXT:    ret

  %c = icmp sgt i8 %a, -1

  %s = select i1 %c, i32 84, i32 -85

  ret i32 %s

}



define i32 @icmpasreq(i32 %input, i32 %a, i32 %b) {

; CHECK-LABEL: icmpasreq:

; CHECK:       // %bb.0:

; CHECK-NEXT:    mov w8, #-1

; CHECK-NEXT:    cmp w8, w0, asr #31

; CHECK-NEXT:    csel w0, w1, w2, eq

; CHECK-NEXT:    ret

  %sh = ashr i32 %input, 31

  %c = icmp eq i32 %sh, -1

  %s = select i1 %c, i32 %a, i32 %b

  ret i32 %s

}



define i32 @icmpasrne(i32 %input, i32 %a, i32 %b) {

; CHECK-LABEL: icmpasrne:

; CHECK:       // %bb.0:

; CHECK-NEXT:    mov w8, #-1

; CHECK-NEXT:    cmp w8, w0, asr #31

; CHECK-NEXT:    csel w0, w1, w2, ne

; CHECK-NEXT:    ret

  %sh = ashr i32 %input, 31

  %c = icmp ne i32 %sh, -1

  %s = select i1 %c, i32 %a, i32 %b

  ret i32 %s

}



define i32 @selecti32i32_0(i32 %a) {

; CHECK-LABEL: selecti32i32_0:

; CHECK:       // %bb.0:

; CHECK-NEXT:    asr w0, w0, #31

; CHECK-NEXT:    ret

  %c = icmp sgt i32 %a, -1

  %s = select i1 %c, i32 0, i32 -1

  ret i32 %s

}



define i32 @selecti32i32_m1(i32 %a) {

; CHECK-LABEL: selecti32i32_m1:

; CHECK:       // %bb.0:

; CHECK-NEXT:    mvn w8, w0

; CHECK-NEXT:    asr w0, w8, #31

; CHECK-NEXT:    ret

  %c = icmp sgt i32 %a, -1

  %s = select i1 %c, i32 -1, i32 0

  ret i32 %s

}



define i32 @selecti32i32_1(i32 %a) {

; CHECK-LABEL: selecti32i32_1:

; CHECK:       // %bb.0:

; CHECK-NEXT:    cmp w0, #0

; CHECK-NEXT:    mov w8, #1

; CHECK-NEXT:    cinv w0, w8, lt

; CHECK-NEXT:    ret

  %c = icmp sgt i32 %a, -1

  %s = select i1 %c, i32 1, i32 -2

  ret i32 %s

}



define i32 @selecti32i32_sge(i32 %a) {

; CHECK-LABEL: selecti32i32_sge:

; CHECK:       // %bb.0:

; CHECK-NEXT:    cmp w0, #0

; CHECK-NEXT:    mov w8, #12

; CHECK-NEXT:    cinv w0, w8, lt

; CHECK-NEXT:    ret

  %c = icmp sge i32 %a, 0

  %s = select i1 %c, i32 12, i32 -13

  ret i32 %s

}



define i32 @selecti32i32_slt(i32 %a) {

; CHECK-LABEL: selecti32i32_slt:

; CHECK:       // %bb.0:

; CHECK-NEXT:    cmp w0, #0

; CHECK-NEXT:    mov w8, #-13

; CHECK-NEXT:    cinv w0, w8, ge

; CHECK-NEXT:    ret

  %c = icmp slt i32 %a, 0

  %s = select i1 %c, i32 -13, i32 12

  ret i32 %s

}



define i32 @selecti32i32_sle(i32 %a) {

; CHECK-LABEL: selecti32i32_sle:

; CHECK:       // %bb.0:

; CHECK-NEXT:    cmp w0, #0

; CHECK-NEXT:    mov w8, #-13

; CHECK-NEXT:    cinv w0, w8, ge

; CHECK-NEXT:    ret

  %c = icmp sle i32 %a, -1

  %s = select i1 %c, i32 -13, i32 12

  ret i32 %s

}



define i32 @selecti32i32_sgt(i32 %a) {

; CHECK-LABEL: selecti32i32_sgt:

; CHECK:       // %bb.0:

; CHECK-NEXT:    cmp w0, #0

; CHECK-NEXT:    mov w8, #-13

; CHECK-NEXT:    cinv w0, w8, ge

; CHECK-NEXT:    ret

  %c = icmp sle i32 %a, -1

  %s = select i1 %c, i32 -13, i32 12

  ret i32 %s

}



define i32 @oneusecmp(i32 %a, i32 %b, i32 %d) {

; CHECK-LABEL: oneusecmp:

; CHECK:       // %bb.0:

; CHECK-NEXT:    cmp w0, #0

; CHECK-NEXT:    mov w8, #-128

; CHECK-NEXT:    cinv w8, w8, ge

; CHECK-NEXT:    csel w9, w2, w1, lt

; CHECK-NEXT:    add w0, w8, w9

; CHECK-NEXT:    ret

  %c = icmp sle i32 %a, -1

  %s = select i1 %c, i32 -128, i32 127

  %s2 = select i1 %c, i32 %d, i32 %b

  %x = add i32 %s, %s2

  ret i32 %x

}

llvm/test/CodeGen/AMDGPU/select-constant-xor.ll

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Original line number Diff line number Diff line 
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py

; RUN: llc -march=amdgcn -mcpu=gfx1010 %s -o - | FileCheck %s



define i32 @xori64i32(i64 %a) {

; CHECK-LABEL: xori64i32:

; CHECK:       ; %bb.0:

; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; CHECK-NEXT:    s_waitcnt_vscnt null, 0x0

; CHECK-NEXT:    v_ashrrev_i32_e32 v0, 31, v1

; CHECK-NEXT:    v_xor_b32_e32 v0, 0x7fffffff, v0

; CHECK-NEXT:    s_setpc_b64 s[30:31]

  %shr4 = ashr i64 %a, 63

  %conv5 = trunc i64 %shr4 to i32

  %xor = xor i32 %conv5, 2147483647

  ret i32 %xor

}



define i64 @selecti64i64(i64 %a) {

; CHECK-LABEL: selecti64i64:

; CHECK:       ; %bb.0:

; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; CHECK-NEXT:    s_waitcnt_vscnt null, 0x0

; CHECK-NEXT:    v_cmp_lt_i64_e32 vcc_lo, -1, v[0:1]

; CHECK-NEXT:    v_bfrev_b32_e32 v2, -2

; CHECK-NEXT:    v_cndmask_b32_e32 v0, 0x80000000, v2, vcc_lo

; CHECK-NEXT:    v_cndmask_b32_e64 v1, -1, 0, vcc_lo

; CHECK-NEXT:    s_setpc_b64 s[30:31]

  %c = icmp sgt i64 %a, -1

  %s = select i1 %c, i64 2147483647, i64 -2147483648

  ret i64 %s

}



define i32 @selecti64i32(i64 %a) {

; CHECK-LABEL: selecti64i32:

; CHECK:       ; %bb.0:

; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; CHECK-NEXT:    s_waitcnt_vscnt null, 0x0

; CHECK-NEXT:    v_cmp_lt_i64_e32 vcc_lo, -1, v[0:1]

; CHECK-NEXT:    v_bfrev_b32_e32 v2, -2

; CHECK-NEXT:    v_cndmask_b32_e32 v0, 0x80000000, v2, vcc_lo

; CHECK-NEXT:    s_setpc_b64 s[30:31]

  %c = icmp sgt i64 %a, -1

  %s = select i1 %c, i32 2147483647, i32 -2147483648

  ret i32 %s

}



define i64 @selecti32i64(i32 %a) {

; CHECK-LABEL: selecti32i64:

; CHECK:       ; %bb.0:

; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; CHECK-NEXT:    s_waitcnt_vscnt null, 0x0

; CHECK-NEXT:    v_bfrev_b32_e32 v1, -2

; CHECK-NEXT:    v_cmp_lt_i32_e32 vcc_lo, -1, v0

; CHECK-NEXT:    v_cndmask_b32_e32 v0, 0x80000000, v1, vcc_lo

; CHECK-NEXT:    v_cndmask_b32_e64 v1, -1, 0, vcc_lo

; CHECK-NEXT:    s_setpc_b64 s[30:31]

  %c = icmp sgt i32 %a, -1

  %s = select i1 %c, i64 2147483647, i64 -2147483648

  ret i64 %s

}







define i8 @xori32i8(i32 %a) {

; CHECK-LABEL: xori32i8:

; CHECK:       ; %bb.0:

; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; CHECK-NEXT:    s_waitcnt_vscnt null, 0x0

; CHECK-NEXT:    v_ashrrev_i32_e32 v0, 31, v0

; CHECK-NEXT:    v_xor_b32_e32 v0, 0x54, v0

; CHECK-NEXT:    s_setpc_b64 s[30:31]

  %shr4 = ashr i32 %a, 31

  %conv5 = trunc i32 %shr4 to i8

  %xor = xor i8 %conv5, 84

  ret i8 %xor

}



define i32 @selecti32i32(i32 %a) {

; CHECK-LABEL: selecti32i32:

; CHECK:       ; %bb.0:

; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; CHECK-NEXT:    s_waitcnt_vscnt null, 0x0

; CHECK-NEXT:    v_mov_b32_e32 v1, 0x54

; CHECK-NEXT:    v_cmp_lt_i32_e32 vcc_lo, -1, v0

; CHECK-NEXT:    v_cndmask_b32_e32 v0, 0xffffffab, v1, vcc_lo

; CHECK-NEXT:    s_setpc_b64 s[30:31]

  %c = icmp sgt i32 %a, -1

  %s = select i1 %c, i32 84, i32 -85

  ret i32 %s

}



define i8 @selecti32i8(i32 %a) {

; CHECK-LABEL: selecti32i8:

; CHECK:       ; %bb.0:

; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; CHECK-NEXT:    s_waitcnt_vscnt null, 0x0

; CHECK-NEXT:    v_mov_b32_e32 v1, 0x54

; CHECK-NEXT:    v_cmp_lt_i32_e32 vcc_lo, -1, v0

; CHECK-NEXT:    v_cndmask_b32_e32 v0, 0xffffffab, v1, vcc_lo

; CHECK-NEXT:    s_setpc_b64 s[30:31]

  %c = icmp sgt i32 %a, -1

  %s = select i1 %c, i8 84, i8 -85

  ret i8 %s

}



define i32 @selecti8i32(i8 %a) {

; CHECK-LABEL: selecti8i32:

; CHECK:       ; %bb.0:

; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; CHECK-NEXT:    s_waitcnt_vscnt null, 0x0

; CHECK-NEXT:    v_mov_b32_e32 v1, -1

; CHECK-NEXT:    v_mov_b32_e32 v2, 0x54

; CHECK-NEXT:    v_cmp_gt_i16_sdwa vcc_lo, sext(v0), v1 src0_sel:BYTE_0 src1_sel:DWORD

; CHECK-NEXT:    v_cndmask_b32_e32 v0, 0xffffffab, v2, vcc_lo

; CHECK-NEXT:    s_setpc_b64 s[30:31]

  %c = icmp sgt i8 %a, -1

  %s = select i1 %c, i32 84, i32 -85

  ret i32 %s

}



define i32 @icmpasreq(i32 %input, i32 %a, i32 %b) {

; CHECK-LABEL: icmpasreq:

; CHECK:       ; %bb.0:

; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; CHECK-NEXT:    s_waitcnt_vscnt null, 0x0

; CHECK-NEXT:    v_ashrrev_i32_e32 v0, 31, v0

; CHECK-NEXT:    v_cmp_eq_u32_e32 vcc_lo, -1, v0

; CHECK-NEXT:    v_cndmask_b32_e32 v0, v2, v1, vcc_lo

; CHECK-NEXT:    s_setpc_b64 s[30:31]

  %sh = ashr i32 %input, 31

  %c = icmp eq i32 %sh, -1

  %s = select i1 %c, i32 %a, i32 %b

  ret i32 %s

}



define i32 @icmpasrne(i32 %input, i32 %a, i32 %b) {

; CHECK-LABEL: icmpasrne:

; CHECK:       ; %bb.0:

; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; CHECK-NEXT:    s_waitcnt_vscnt null, 0x0

; CHECK-NEXT:    v_ashrrev_i32_e32 v0, 31, v0

; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc_lo, -1, v0

; CHECK-NEXT:    v_cndmask_b32_e32 v0, v2, v1, vcc_lo

; CHECK-NEXT:    s_setpc_b64 s[30:31]

  %sh = ashr i32 %input, 31

  %c = icmp ne i32 %sh, -1

  %s = select i1 %c, i32 %a, i32 %b

  ret i32 %s

}



define i32 @oneusecmp(i32 %a, i32 %b, i32 %d) {

; CHECK-LABEL: oneusecmp:

; CHECK:       ; %bb.0:

; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; CHECK-NEXT:    s_waitcnt_vscnt null, 0x0

; CHECK-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 0, v0

; CHECK-NEXT:    v_mov_b32_e32 v3, 0xffffff80

; CHECK-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc_lo

; CHECK-NEXT:    v_cndmask_b32_e32 v0, 0x7f, v3, vcc_lo

; CHECK-NEXT:    v_add_nc_u32_e32 v0, v0, v1

; CHECK-NEXT:    s_setpc_b64 s[30:31]

  %c = icmp sle i32 %a, -1

  %s = select i1 %c, i32 -128, i32 127

  %s2 = select i1 %c, i32 %d, i32 %b

  %x = add i32 %s, %s2

  ret i32 %x

}

llvm/test/CodeGen/AMDGPU/selectcc-icmp-select-float.ll

+19 −4
Original line number Diff line number Diff line 
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py

; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s



; Note additional optimizations may cause this SGT to be replaced with a

; CND* instruction.

; CHECK: SETGT_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, literal.x,

; CHECK-NEXT: -1

; Test a selectcc with i32 LHS/RHS and float True/False



define amdgpu_kernel void @test(float addrspace(1)* %out, i32 addrspace(1)* %in) {

; CHECK-LABEL: test:

; CHECK:       ; %bb.0: ; %entry

; CHECK-NEXT:    ALU 0, @8, KC0[CB0:0-32], KC1[]

; CHECK-NEXT:    TEX 0 @6

; CHECK-NEXT:    ALU 4, @9, KC0[CB0:0-32], KC1[]

; CHECK-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1

; CHECK-NEXT:    CF_END

; CHECK-NEXT:    PAD

; CHECK-NEXT:    Fetch clause starting at 6:

; CHECK-NEXT:     VTX_READ_32 T0.X, T0.X, 0, #1

; CHECK-NEXT:    ALU clause starting at 8:

; CHECK-NEXT:     MOV * T0.X, KC0[2].Z,

; CHECK-NEXT:    ALU clause starting at 9:

; CHECK-NEXT:     SETGT_INT * T0.W, T0.X, literal.x,

; CHECK-NEXT:    -1(nan), 0(0.000000e+00)

; CHECK-NEXT:     CNDE_INT T0.X, PV.W, 0.0, literal.x,

; CHECK-NEXT:     LSHR * T1.X, KC0[2].Y, literal.y,

; CHECK-NEXT:    1065353216(1.000000e+00), 2(2.802597e-45)

entry:

  %0 = load i32, i32 addrspace(1)* %in

  %1 = icmp sge i32 %0, 0

llvm/test/CodeGen/ARM/select-constant-xor.ll

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File added.

Preview size limit exceeded, changes collapsed.

llvm/test/CodeGen/PowerPC/select-constant-xor.ll

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Original line number Diff line number Diff line 
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py

; RUN: llc -mcpu=pwr8 -mtriple=powerpc64-unknown-unknown %s -o - | FileCheck %s



define i32 @xori64i32(i64 %a) {

; CHECK-LABEL: xori64i32:

; CHECK:       # %bb.0:

; CHECK-NEXT:    sradi 3, 3, 63

; CHECK-NEXT:    xori 3, 3, 65535

; CHECK-NEXT:    xoris 3, 3, 32767

; CHECK-NEXT:    blr

  %shr4 = ashr i64 %a, 63

  %conv5 = trunc i64 %shr4 to i32

  %xor = xor i32 %conv5, 2147483647

  ret i32 %xor

}



define i64 @selecti64i64(i64 %a) {

; CHECK-LABEL: selecti64i64:

; CHECK:       # %bb.0:

; CHECK-NEXT:    lis 4, 32767

; CHECK-NEXT:    cmpdi 3, -1

; CHECK-NEXT:    ori 3, 4, 65535

; CHECK-NEXT:    lis 4, -32768

; CHECK-NEXT:    iselgt 3, 3, 4

; CHECK-NEXT:    blr

  %c = icmp sgt i64 %a, -1

  %s = select i1 %c, i64 2147483647, i64 -2147483648

  ret i64 %s

}



define i32 @selecti64i32(i64 %a) {

; CHECK-LABEL: selecti64i32:

; CHECK:       # %bb.0:

; CHECK-NEXT:    lis 4, 32767

; CHECK-NEXT:    cmpdi 3, -1

; CHECK-NEXT:    ori 3, 4, 65535

; CHECK-NEXT:    lis 4, -32768

; CHECK-NEXT:    iselgt 3, 3, 4

; CHECK-NEXT:    blr

  %c = icmp sgt i64 %a, -1

  %s = select i1 %c, i32 2147483647, i32 -2147483648

  ret i32 %s

}



define i64 @selecti32i64(i32 %a) {

; CHECK-LABEL: selecti32i64:

; CHECK:       # %bb.0:

; CHECK-NEXT:    lis 4, 32767

; CHECK-NEXT:    cmpwi 3, -1

; CHECK-NEXT:    ori 3, 4, 65535

; CHECK-NEXT:    lis 4, -32768

; CHECK-NEXT:    iselgt 3, 3, 4

; CHECK-NEXT:    blr

  %c = icmp sgt i32 %a, -1

  %s = select i1 %c, i64 2147483647, i64 -2147483648

  ret i64 %s

}







define i8 @xori32i8(i32 %a) {

; CHECK-LABEL: xori32i8:

; CHECK:       # %bb.0:

; CHECK-NEXT:    srawi 3, 3, 31

; CHECK-NEXT:    xori 3, 3, 84

; CHECK-NEXT:    blr

  %shr4 = ashr i32 %a, 31

  %conv5 = trunc i32 %shr4 to i8

  %xor = xor i8 %conv5, 84

  ret i8 %xor

}



define i32 @selecti32i32(i32 %a) {

; CHECK-LABEL: selecti32i32:

; CHECK:       # %bb.0:

; CHECK-NEXT:    li 4, -85

; CHECK-NEXT:    cmpwi 3, -1

; CHECK-NEXT:    li 3, 84

; CHECK-NEXT:    iselgt 3, 3, 4

; CHECK-NEXT:    blr

  %c = icmp sgt i32 %a, -1

  %s = select i1 %c, i32 84, i32 -85

  ret i32 %s

}



define i8 @selecti32i8(i32 %a) {

; CHECK-LABEL: selecti32i8:

; CHECK:       # %bb.0:

; CHECK-NEXT:    li 4, -85

; CHECK-NEXT:    cmpwi 3, -1

; CHECK-NEXT:    li 3, 84

; CHECK-NEXT:    iselgt 3, 3, 4

; CHECK-NEXT:    blr

  %c = icmp sgt i32 %a, -1

  %s = select i1 %c, i8 84, i8 -85

  ret i8 %s

}



define i32 @selecti8i32(i8 %a) {

; CHECK-LABEL: selecti8i32:

; CHECK:       # %bb.0:

; CHECK-NEXT:    extsb 3, 3

; CHECK-NEXT:    li 4, -85

; CHECK-NEXT:    cmpwi 3, -1

; CHECK-NEXT:    li 3, 84

; CHECK-NEXT:    iselgt 3, 3, 4

; CHECK-NEXT:    blr

  %c = icmp sgt i8 %a, -1

  %s = select i1 %c, i32 84, i32 -85

  ret i32 %s

}



define i32 @icmpasreq(i32 %input, i32 %a, i32 %b) {

; CHECK-LABEL: icmpasreq:

; CHECK:       # %bb.0:

; CHECK-NEXT:    srawi 3, 3, 31

; CHECK-NEXT:    cmpwi 3, -1

; CHECK-NEXT:    iseleq 3, 4, 5

; CHECK-NEXT:    blr

  %sh = ashr i32 %input, 31

  %c = icmp eq i32 %sh, -1

  %s = select i1 %c, i32 %a, i32 %b

  ret i32 %s

}



define i32 @icmpasrne(i32 %input, i32 %a, i32 %b) {

; CHECK-LABEL: icmpasrne:

; CHECK:       # %bb.0:

; CHECK-NEXT:    srawi 3, 3, 31

; CHECK-NEXT:    cmpwi 3, -1

; CHECK-NEXT:    iseleq 3, 5, 4

; CHECK-NEXT:    blr

  %sh = ashr i32 %input, 31

  %c = icmp ne i32 %sh, -1

  %s = select i1 %c, i32 %a, i32 %b

  ret i32 %s

}



define i32 @oneusecmp(i32 %a, i32 %b, i32 %d) {

; CHECK-LABEL: oneusecmp:

; CHECK:       # %bb.0:

; CHECK-NEXT:    li 6, 127

; CHECK-NEXT:    cmpwi 3, 0

; CHECK-NEXT:    li 3, -128

; CHECK-NEXT:    isellt 3, 3, 6

; CHECK-NEXT:    isellt 4, 5, 4

; CHECK-NEXT:    add 3, 3, 4

; CHECK-NEXT:    blr

  %c = icmp sle i32 %a, -1

  %s = select i1 %c, i32 -128, i32 127

  %s2 = select i1 %c, i32 %d, i32 %b

  %x = add i32 %s, %s2

  ret i32 %x

}