Commit 77b7b23c authored by Amaury Séchet's avatar Amaury Séchet
Browse files

Automatically generated arm64-abi-varargs.ll . NFC

parent 8cdfdfee

llvm/test/CodeGen/AArch64/arm64-abi-varargs.ll

+122 −28
Original line number Diff line number Diff line 
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py

; RUN: llc < %s -mtriple=arm64-apple-ios7.0.0 -mcpu=cyclone -enable-misched=false | FileCheck %s



; rdar://13625505
@@ -5,15 +6,25 @@ 
; varargs start right after at 8-byte alignment.

define void @fn9(i32* %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, i32 %a6, i32 %a7, i32 %a8, i32 %a9, ...) nounwind noinline ssp {

; CHECK-LABEL: fn9:

; 9th fixed argument

; CHECK: ldr {{w[0-9]+}}, [sp, #64]

; CHECK-DAG: add [[ARGS:x[0-9]+]], sp, #72

; First vararg

; CHECK-DAG: ldr {{w[0-9]+}}, [sp, #72]

; Second vararg

; CHECK-DAG: ldr {{w[0-9]+}}, [sp, #80]

; Third vararg

; CHECK-DAG: ldr {{w[0-9]+}}, [sp, #88]

; CHECK:       ; %bb.0:

; CHECK-NEXT:    sub sp, sp, #64 ; =64

; CHECK-NEXT:    ldr w8, [sp, #64]

; CHECK-NEXT:    stp w2, w1, [sp, #52]

; CHECK-NEXT:    stp w4, w3, [sp, #44]

; CHECK-NEXT:    stp w6, w5, [sp, #36]

; CHECK-NEXT:    str w7, [sp, #32]

; CHECK-NEXT:    str w8, [x0]

; CHECK-NEXT:    ldr w8, [sp, #72]

; CHECK-NEXT:    str w8, [sp, #20]

; CHECK-NEXT:    ldr w8, [sp, #80]

; CHECK-NEXT:    str w8, [sp, #16]

; CHECK-NEXT:    add x8, sp, #72 ; =72

; CHECK-NEXT:    add x8, x8, #24 ; =24

; CHECK-NEXT:    str x8, [sp, #24]

; CHECK-NEXT:    ldr w8, [sp, #88]

; CHECK-NEXT:    str w8, [sp, #12]

; CHECK-NEXT:    add sp, sp, #64 ; =64

; CHECK-NEXT:    ret

  %1 = alloca i32, align 4

  %2 = alloca i32, align 4

  %3 = alloca i32, align 4
@@ -51,9 +62,47 @@ declare void @llvm.va_start(i8*) nounwind 


define i32 @main() nounwind ssp {

; CHECK-LABEL: main:

; CHECK: stp {{x[0-9]+}}, {{x[0-9]+}}, [sp, #16]

; CHECK: str {{x[0-9]+}}, [sp, #8]

; CHECK: str {{w[0-9]+}}, [sp]

; CHECK:       ; %bb.0:

; CHECK-NEXT:    sub sp, sp, #96 ; =96

; CHECK-NEXT:    stp x29, x30, [sp, #80] ; 16-byte Folded Spill

; CHECK-NEXT:    mov w8, #1

; CHECK-NEXT:    str w8, [sp, #76]

; CHECK-NEXT:    mov w8, #2

; CHECK-NEXT:    str w8, [sp, #72]

; CHECK-NEXT:    mov w8, #3

; CHECK-NEXT:    str w8, [sp, #68]

; CHECK-NEXT:    mov w8, #4

; CHECK-NEXT:    str w8, [sp, #64]

; CHECK-NEXT:    mov w8, #5

; CHECK-NEXT:    str w8, [sp, #60]

; CHECK-NEXT:    mov w8, #6

; CHECK-NEXT:    str w8, [sp, #56]

; CHECK-NEXT:    mov w8, #7

; CHECK-NEXT:    str w8, [sp, #52]

; CHECK-NEXT:    mov w8, #8

; CHECK-NEXT:    str w8, [sp, #48]

; CHECK-NEXT:    mov w8, #9

; CHECK-NEXT:    mov w9, #10

; CHECK-NEXT:    stp w9, w8, [sp, #40]

; CHECK-NEXT:    mov w10, #11

; CHECK-NEXT:    mov w11, #12

; CHECK-NEXT:    stp w11, w10, [sp, #32]

; CHECK-NEXT:    stp x10, x11, [sp, #16]

; CHECK-NEXT:    str x9, [sp, #8]

; CHECK-NEXT:    str w8, [sp]

; CHECK-NEXT:    add x0, sp, #76 ; =76

; CHECK-NEXT:    mov w1, #2

; CHECK-NEXT:    mov w2, #3

; CHECK-NEXT:    mov w3, #4

; CHECK-NEXT:    mov w4, #5

; CHECK-NEXT:    mov w5, #6

; CHECK-NEXT:    mov w6, #7

; CHECK-NEXT:    mov w7, #8

; CHECK-NEXT:    bl _fn9

; CHECK-NEXT:    mov w0, #0

; CHECK-NEXT:    ldp x29, x30, [sp, #80] ; 16-byte Folded Reload

; CHECK-NEXT:    add sp, sp, #96 ; =96

; CHECK-NEXT:    ret

  %a1 = alloca i32, align 4

  %a2 = alloca i32, align 4

  %a3 = alloca i32, align 4
@@ -97,12 +146,20 @@ define i32 @main() nounwind ssp { 
;rdar://13668483

@.str = private unnamed_addr constant [4 x i8] c"fmt\00", align 1

define void @foo(i8* %fmt, ...) nounwind {

entry:

; CHECK-LABEL: foo:

; CHECK: ldr {{w[0-9]+}}, [sp, #48]

; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, #23

; CHECK: and x[[ADDR:[0-9]+]], {{x[0-9]+}}, #0xfffffffffffffff0

; CHECK: ldr {{q[0-9]+}}, [x[[ADDR]]]

; CHECK:       ; %bb.0: ; %entry

; CHECK-NEXT:    sub sp, sp, #48 ; =48

; CHECK-NEXT:    ldr w8, [sp, #48]

; CHECK-NEXT:    str w8, [sp, #28]

; CHECK-NEXT:    add x8, sp, #48 ; =48

; CHECK-NEXT:    add x8, x8, #23 ; =23

; CHECK-NEXT:    and x8, x8, #0xfffffffffffffff0

; CHECK-NEXT:    add x9, x8, #16 ; =16

; CHECK-NEXT:    stp x9, x0, [sp, #32]

; CHECK-NEXT:    ldr q0, [x8]

; CHECK-NEXT:    str q0, [sp], #48

; CHECK-NEXT:    ret

entry:

  %fmt.addr = alloca i8*, align 8

  %args = alloca i8*, align 8

  %vc = alloca i32, align 4
@@ -118,10 +175,24 @@ entry: 
}



define void @bar(i32 %x, <4 x i32> %y) nounwind {

entry:

; CHECK-LABEL: bar:

; CHECK: stp {{q[0-9]+}}, {{q[0-9]+}}, [sp, #16]

; CHECK: str {{x[0-9]+}}, [sp]

; CHECK:       ; %bb.0: ; %entry

; CHECK-NEXT:    sub sp, sp, #80 ; =80

; CHECK-NEXT:    stp x29, x30, [sp, #64] ; 16-byte Folded Spill

; CHECK-NEXT:    ; kill: def $w0 killed $w0 def $x0

; CHECK-NEXT:    str w0, [sp, #60]

; CHECK-NEXT:    stp q0, q0, [sp, #16]

; CHECK-NEXT:    str x0, [sp]

; CHECK-NEXT:  Lloh0:

; CHECK-NEXT:    adrp x0, l_.str@PAGE

; CHECK-NEXT:  Lloh1:

; CHECK-NEXT:    add x0, x0, l_.str@PAGEOFF

; CHECK-NEXT:    bl _foo

; CHECK-NEXT:    ldp x29, x30, [sp, #64] ; 16-byte Folded Reload

; CHECK-NEXT:    add sp, sp, #80 ; =80

; CHECK-NEXT:    ret

; CHECK-NEXT:    .loh AdrpAdd Lloh0, Lloh1

entry:

  %x.addr = alloca i32, align 4

  %y.addr = alloca <4 x i32>, align 16

  store i32 %x, i32* %x.addr, align 4
@@ -137,12 +208,20 @@ entry: 
; side is 16-byte aligned on stack.

%struct.s41 = type { i32, i16, i32, i16 }

define void @foo2(i8* %fmt, ...) nounwind {

entry:

; CHECK-LABEL: foo2:

; CHECK: ldr {{w[0-9]+}}, [sp, #48]

; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, #23

; CHECK: and x[[ADDR:[0-9]+]], {{x[0-9]+}}, #0xfffffffffffffff0

; CHECK: ldr {{q[0-9]+}}, [x[[ADDR]]]

; CHECK:       ; %bb.0: ; %entry

; CHECK-NEXT:    sub sp, sp, #48 ; =48

; CHECK-NEXT:    ldr w8, [sp, #48]

; CHECK-NEXT:    str w8, [sp, #28]

; CHECK-NEXT:    add x8, sp, #48 ; =48

; CHECK-NEXT:    add x8, x8, #23 ; =23

; CHECK-NEXT:    and x8, x8, #0xfffffffffffffff0

; CHECK-NEXT:    add x9, x8, #16 ; =16

; CHECK-NEXT:    stp x9, x0, [sp, #32]

; CHECK-NEXT:    ldr q0, [x8]

; CHECK-NEXT:    str q0, [sp], #48

; CHECK-NEXT:    ret

entry:

  %fmt.addr = alloca i8*, align 8

  %args = alloca i8*, align 8

  %vc = alloca i32, align 4
@@ -168,10 +247,25 @@ entry: 
declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i1) nounwind



define void @bar2(i32 %x, i128 %s41.coerce) nounwind {

entry:

; CHECK-LABEL: bar2:

; CHECK: stp {{x[0-9]+}}, {{x[0-9]+}}, [sp, #16]

; CHECK: str {{x[0-9]+}}, [sp]

; CHECK:       ; %bb.0: ; %entry

; CHECK-NEXT:    sub sp, sp, #80 ; =80

; CHECK-NEXT:    stp x29, x30, [sp, #64] ; 16-byte Folded Spill

; CHECK-NEXT:    ; kill: def $w0 killed $w0 def $x0

; CHECK-NEXT:    str w0, [sp, #60]

; CHECK-NEXT:    stp x1, x2, [sp, #32]

; CHECK-NEXT:    stp x1, x2, [sp, #16]

; CHECK-NEXT:    str x0, [sp]

; CHECK-NEXT:  Lloh2:

; CHECK-NEXT:    adrp x0, l_.str@PAGE

; CHECK-NEXT:  Lloh3:

; CHECK-NEXT:    add x0, x0, l_.str@PAGEOFF

; CHECK-NEXT:    bl _foo2

; CHECK-NEXT:    ldp x29, x30, [sp, #64] ; 16-byte Folded Reload

; CHECK-NEXT:    add sp, sp, #80 ; =80

; CHECK-NEXT:    ret

; CHECK-NEXT:    .loh AdrpAdd Lloh2, Lloh3

entry:

  %x.addr = alloca i32, align 4

  %s41 = alloca %struct.s41, align 16

  store i32 %x, i32* %x.addr, align 4