Commit 77ad1dc5 authored by Bill Wendling's avatar Bill Wendling
Browse files

Rename the narrow shift right immediate operands to "shr_imm*" operands. Also 

expand the testing of the narrowing shift right instructions.

No functionality change.

llvm-svn: 127193
parent 71c380f6

llvm/lib/Target/ARM/ARMCodeEmitter.cpp

+5 −3
Original line number Diff line number Diff line
@@ -312,11 +312,13 @@ namespace { 
    unsigned getRegisterListOpValue(const MachineInstr &MI, unsigned Op)

      const { return 0; }



    unsigned getNarrowShiftRight16Imm(const MachineInstr &MI, unsigned Op)

    unsigned getShiftRight8Imm(const MachineInstr &MI, unsigned Op)

      const { return 0; }

    unsigned getNarrowShiftRight32Imm(const MachineInstr &MI, unsigned Op)

    unsigned getShiftRight16Imm(const MachineInstr &MI, unsigned Op)

      const { return 0; }

    unsigned getNarrowShiftRight64Imm(const MachineInstr &MI, unsigned Op)

    unsigned getShiftRight32Imm(const MachineInstr &MI, unsigned Op)

      const { return 0; }

    unsigned getShiftRight64Imm(const MachineInstr &MI, unsigned Op)

      const { return 0; }



    /// getMovi32Value - Return binary encoding of operand for movw/movt. If the

llvm/lib/Target/ARM/ARMInstrFormats.td

+18 −13
Original line number Diff line number Diff line
@@ -221,20 +221,25 @@ def neg_zero : Operand<i32> { 
  let PrintMethod = "printNegZeroOperand";

}



// Narrow Shift Right Immediate - A narrow shift right immediate is encoded

// differently from other shift immediates. The imm6 field is encoded like so:

// Shift Right Immediate - A shift right immediate is encoded differently from

// other shift immediates. The imm6 field is encoded like so:

//

//   16-bit: imm6<5:3> = '001', 8 - <imm> is encded in imm6<2:0>

//   32-bit: imm6<5:4> = '01',16 - <imm> is encded in imm6<3:0>

//   64-bit: imm6<5> = '1', 32 - <imm> is encded in imm6<4:0>

def nsr16_imm : Operand<i32> {

  let EncoderMethod = "getNarrowShiftRight16Imm";

}

def nsr32_imm : Operand<i32> {

  let EncoderMethod = "getNarrowShiftRight32Imm";

}

def nsr64_imm : Operand<i32> {

  let EncoderMethod = "getNarrowShiftRight64Imm";

//    Offset    Encoding

//     8        imm6<5:3> = '001', 8 - <imm> is encoded in imm6<2:0>

//     16       imm6<5:4> = '01', 16 - <imm> is encoded in imm6<3:0>

//     32       imm6<5> = '1', 32 - <imm> is encoded in imm6<4:0>

//     64       64 - <imm> is encoded in imm6<5:0>

def shr_imm8  : Operand<i32> {

  let EncoderMethod = "getShiftRight8Imm";

}

def shr_imm16 : Operand<i32> {

  let EncoderMethod = "getShiftRight16Imm";

}

def shr_imm32 : Operand<i32> {

  let EncoderMethod = "getShiftRight32Imm";

}

def shr_imm64 : Operand<i32> {

  let EncoderMethod = "getShiftRight64Imm";

}



//===----------------------------------------------------------------------===//

llvm/lib/Target/ARM/ARMInstrNEON.td

+3 −3
Original line number Diff line number Diff line
@@ -3154,17 +3154,17 @@ multiclass N2VNSh_HSD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, 
                      SDNode OpNode> {

  def v8i8 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,

                    OpcodeStr, !strconcat(Dt, "16"),

                    v8i8, v8i16, nsr16_imm, OpNode> {

                    v8i8, v8i16, shr_imm8, OpNode> {

    let Inst{21-19} = 0b001; // imm6 = 001xxx

  }

  def v4i16 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,

                     OpcodeStr, !strconcat(Dt, "32"),

                     v4i16, v4i32, nsr32_imm, OpNode> {

                     v4i16, v4i32, shr_imm16, OpNode> {

    let Inst{21-20} = 0b01;  // imm6 = 01xxxx

  }

  def v2i32 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,

                     OpcodeStr, !strconcat(Dt, "64"),

                     v2i32, v2i64, nsr64_imm, OpNode> {

                     v2i32, v2i64, shr_imm32, OpNode> {

    let Inst{21} = 0b1;      // imm6 = 1xxxxx

  }

}

llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp

+20 −12
Original line number Diff line number Diff line
@@ -278,11 +278,13 @@ public: 
  unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,

                                     SmallVectorImpl<MCFixup> &Fixups) const;



  unsigned getNarrowShiftRight16Imm(const MCInst &MI, unsigned Op,

  unsigned getShiftRight8Imm(const MCInst &MI, unsigned Op,

                             SmallVectorImpl<MCFixup> &Fixups) const;

  unsigned getNarrowShiftRight32Imm(const MCInst &MI, unsigned Op,

  unsigned getShiftRight16Imm(const MCInst &MI, unsigned Op,

                              SmallVectorImpl<MCFixup> &Fixups) const;

  unsigned getNarrowShiftRight64Imm(const MCInst &MI, unsigned Op,

  unsigned getShiftRight32Imm(const MCInst &MI, unsigned Op,

                              SmallVectorImpl<MCFixup> &Fixups) const;

  unsigned getShiftRight64Imm(const MCInst &MI, unsigned Op,

                              SmallVectorImpl<MCFixup> &Fixups) const;



  unsigned NEONThumb2DataIPostEncoder(const MCInst &MI,
@@ -1209,23 +1211,29 @@ getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op, 
}



unsigned ARMMCCodeEmitter::

getNarrowShiftRight16Imm(const MCInst &MI, unsigned Op,

getShiftRight8Imm(const MCInst &MI, unsigned Op,

                  SmallVectorImpl<MCFixup> &Fixups) const {

  return 8 - MI.getOperand(Op).getImm();

}



unsigned ARMMCCodeEmitter::

getNarrowShiftRight32Imm(const MCInst &MI, unsigned Op,

getShiftRight16Imm(const MCInst &MI, unsigned Op,

                   SmallVectorImpl<MCFixup> &Fixups) const {

  return 16 - MI.getOperand(Op).getImm();

}



unsigned ARMMCCodeEmitter::

getNarrowShiftRight64Imm(const MCInst &MI, unsigned Op,

getShiftRight32Imm(const MCInst &MI, unsigned Op,

                   SmallVectorImpl<MCFixup> &Fixups) const {

  return 32 - MI.getOperand(Op).getImm();

}



unsigned ARMMCCodeEmitter::

getShiftRight64Imm(const MCInst &MI, unsigned Op,

                   SmallVectorImpl<MCFixup> &Fixups) const {

  return 64 - MI.getOperand(Op).getImm();

}



void ARMMCCodeEmitter::

EncodeInstruction(const MCInst &MI, raw_ostream &OS,

                  SmallVectorImpl<MCFixup> &Fixups) const {

llvm/test/MC/ARM/neon-shift-encoding.s

+5 −0
Original line number Diff line number Diff line
@@ -158,5 +158,10 @@ 
	vrshrn.i32	d16, q8, #16

@ CHECK: vrshrn.i64	d16, q8, #32    @ encoding: [0x70,0x08,0xe0,0xf2]

	vrshrn.i64	d16, q8, #32



@ CHECK: vqrshrn.s16	d16, q8, #4     @ encoding: [0x70,0x09,0xcc,0xf2]

        vqrshrn.s16	d16, q8, #4

@ CHECK: vqrshrn.s32	d16, q8, #13    @ encoding: [0x70,0x09,0xd3,0xf2]

        vqrshrn.s32	d16, q8, #13

@ CHECK: vqrshrn.s64	d16, q8, #13    @ encoding: [0x70,0x09,0xf3,0xf2]

        vqrshrn.s64	d16, q8, #13