Commit 77105d98 authored by Daniel Sanders's avatar Daniel Sanders
Browse files

Merging r227089: 

------------------------------------------------------------------------
r227089 | vkalintiris | 2015-01-26 12:33:22 +0000 (Mon, 26 Jan 2015) | 15 lines

[mips] Enable arithmetic and binary operations for the i128 data type.

Summary:
This patch adds support for some operations that were missing from
128-bit integer types (add/sub/mul/sdiv/udiv... etc.). With these
changes we can support the __int128_t and __uint128_t data types
from C/C++.

Depends on D7125

Reviewers: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D7143
------------------------------------------------------------------------

llvm-svn: 231471
parent 2a764cb0

llvm/lib/Target/Mips/Mips64InstrInfo.td

+10 −0
Original line number Diff line number Diff line
@@ -438,6 +438,16 @@ def : MipsPat<(i64 (sext_inreg GPR64:$src, i32)), 
// bswap MipsPattern

def : MipsPat<(bswap GPR64:$rt), (DSHD (DSBH GPR64:$rt))>;



// Carry pattern

def : MipsPat<(subc GPR64:$lhs, GPR64:$rhs),

              (DSUBu GPR64:$lhs, GPR64:$rhs)>;

let AdditionalPredicates = [NotDSP] in {

  def : MipsPat<(addc GPR64:$lhs, GPR64:$rhs),

                (DADDu GPR64:$lhs, GPR64:$rhs)>;

  def : MipsPat<(addc GPR64:$lhs, immSExt16:$imm),

                (DADDiu GPR64:$lhs, imm:$imm)>;

}



//===----------------------------------------------------------------------===//

// Instruction aliases

//===----------------------------------------------------------------------===//

llvm/lib/Target/Mips/MipsISelLowering.cpp

+28 −26
Original line number Diff line number Diff line
@@ -257,6 +257,9 @@ MipsTargetLowering::MipsTargetLowering(MipsTargetMachine &TM, 
    setOperationAction(ISD::LOAD,               MVT::i64,   Custom);

    setOperationAction(ISD::STORE,              MVT::i64,   Custom);

    setOperationAction(ISD::FP_TO_SINT,         MVT::i64,   Custom);

    setOperationAction(ISD::SHL_PARTS,          MVT::i64,   Custom);

    setOperationAction(ISD::SRA_PARTS,          MVT::i64,   Custom);

    setOperationAction(ISD::SRL_PARTS,          MVT::i64,   Custom);

  }



  if (!Subtarget.isGP64bit()) {
@@ -1992,10 +1995,11 @@ SDValue MipsTargetLowering::lowerATOMIC_FENCE(SDValue Op, 
SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op,

                                                SelectionDAG &DAG) const {

  SDLoc DL(Op);

  MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32;



  SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);

  SDValue Shamt = Op.getOperand(2);



  // if shamt < 32:

  // if shamt < (VT.bits):

  //  lo = (shl lo, shamt)

  //  hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt))

  // else:
@@ -2003,18 +2007,17 @@ SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op, 
  //  hi = (shl lo, shamt[4:0])

  SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,

                            DAG.getConstant(-1, MVT::i32));

  SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo,

                                      DAG.getConstant(1, MVT::i32));

  SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, ShiftRight1Lo,

                                     Not);

  SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi, Shamt);

  SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo);

  SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, MVT::i32, Lo, Shamt);

  SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo,

                                      DAG.getConstant(1, VT));

  SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, Not);

  SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt);

  SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);

  SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt);

  SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,

                             DAG.getConstant(0x20, MVT::i32));

  Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond,

                   DAG.getConstant(0, MVT::i32), ShiftLeftLo);

  Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftLeftLo, Or);

  Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond,

                   DAG.getConstant(0, VT), ShiftLeftLo);

  Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftLeftLo, Or);



  SDValue Ops[2] = {Lo, Hi};

  return DAG.getMergeValues(Ops, DL);
@@ -2025,8 +2028,9 @@ SDValue MipsTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, 
  SDLoc DL(Op);

  SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);

  SDValue Shamt = Op.getOperand(2);

  MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32;



  // if shamt < 32:

  // if shamt < (VT.bits):

  //  lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt))

  //  if isSRA:

  //    hi = (sra hi, shamt)
@@ -2041,21 +2045,19 @@ SDValue MipsTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, 
  //   hi = 0

  SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,

                            DAG.getConstant(-1, MVT::i32));

  SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi,

                                     DAG.getConstant(1, MVT::i32));

  SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, ShiftLeft1Hi, Not);

  SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo, Shamt);

  SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo);

  SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, DL, MVT::i32,

                                     Hi, Shamt);

  SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, VT, Hi,

                                     DAG.getConstant(1, VT));

  SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, ShiftLeft1Hi, Not);

  SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt);

  SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);

  SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL,

                                     DL, VT, Hi, Shamt);

  SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,

                             DAG.getConstant(0x20, MVT::i32));

  SDValue Shift31 = DAG.getNode(ISD::SRA, DL, MVT::i32, Hi,

                                DAG.getConstant(31, MVT::i32));

  Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftRightHi, Or);

  Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond,

                   IsSRA ? Shift31 : DAG.getConstant(0, MVT::i32),

                   ShiftRightHi);

  SDValue Shift31 = DAG.getNode(ISD::SRA, DL, VT, Hi, DAG.getConstant(31, VT));

  Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftRightHi, Or);

  Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond,

                   IsSRA ? Shift31 : DAG.getConstant(0, VT), ShiftRightHi);



  SDValue Ops[2] = {Lo, Hi};

  return DAG.getMergeValues(Ops, DL);

llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp

+24 −4
Original line number Diff line number Diff line
@@ -239,13 +239,31 @@ SDNode *MipsSEDAGToDAGISel::selectAddESubE(unsigned MOp, SDValue InFlag, 
          (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&

         "(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn");



  unsigned SLTuOp = Mips::SLTu, ADDuOp = Mips::ADDu;

  if (Subtarget->isGP64bit()) {

    SLTuOp = Mips::SLTu64;

    ADDuOp = Mips::DADDu;

  }



  SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) };

  SDValue LHS = Node->getOperand(0), RHS = Node->getOperand(1);

  EVT VT = LHS.getValueType();



  SDNode *Carry = CurDAG->getMachineNode(Mips::SLTu, DL, VT, Ops);

  SDNode *AddCarry = CurDAG->getMachineNode(Mips::ADDu, DL, VT,

  SDNode *Carry = CurDAG->getMachineNode(SLTuOp, DL, VT, Ops);



  if (Subtarget->isGP64bit()) {

    // On 64-bit targets, sltu produces an i64 but our backend currently says

    // that SLTu64 produces an i32. We need to fix this in the long run but for

    // now, just make the DAG type-correct by asserting the upper bits are zero.

    Carry = CurDAG->getMachineNode(Mips::SUBREG_TO_REG, DL, VT,

                                   CurDAG->getTargetConstant(0, VT),

                                   SDValue(Carry, 0),

                                   CurDAG->getTargetConstant(Mips::sub_32, VT));

  }



  SDNode *AddCarry = CurDAG->getMachineNode(ADDuOp, DL, VT,

                                            SDValue(Carry, 0), RHS);



  return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue, LHS,

                              SDValue(AddCarry, 0));

}
@@ -644,7 +662,8 @@ std::pair<bool, SDNode*> MipsSEDAGToDAGISel::selectNode(SDNode *Node) { 


  case ISD::SUBE: {

    SDValue InFlag = Node->getOperand(2);

    Result = selectAddESubE(Mips::SUBu, InFlag, InFlag.getOperand(0), DL, Node);

    unsigned Opc = Subtarget->isGP64bit() ? Mips::DSUBu : Mips::SUBu;

    Result = selectAddESubE(Opc, InFlag, InFlag.getOperand(0), DL, Node);

    return std::make_pair(true, Result);

  }
@@ -652,7 +671,8 @@ std::pair<bool, SDNode*> MipsSEDAGToDAGISel::selectNode(SDNode *Node) { 
    if (Subtarget->hasDSP()) // Select DSP instructions, ADDSC and ADDWC.

      break;

    SDValue InFlag = Node->getOperand(2);

    Result = selectAddESubE(Mips::ADDu, InFlag, InFlag.getValue(0), DL, Node);

    unsigned Opc = Subtarget->isGP64bit() ? Mips::DADDu : Mips::ADDu;

    Result = selectAddESubE(Opc, InFlag, InFlag.getValue(0), DL, Node);

    return std::make_pair(true, Result);

  }

llvm/lib/Target/Mips/MipsSEISelLowering.cpp

+4 −0
Original line number Diff line number Diff line
@@ -125,6 +125,8 @@ MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM, 
    setOperationAction(ISD::MUL,              MVT::i64, Custom);



  if (Subtarget.isGP64bit()) {

    setOperationAction(ISD::SMUL_LOHI,        MVT::i64, Custom);

    setOperationAction(ISD::UMUL_LOHI,        MVT::i64, Custom);

    setOperationAction(ISD::MULHS,            MVT::i64, Custom);

    setOperationAction(ISD::MULHU,            MVT::i64, Custom);

  }
@@ -203,6 +205,8 @@ MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM, 
  if (Subtarget.hasMips64r6()) {

    // MIPS64r6 replaces the accumulator-based multiplies with a three register

    // instruction

    setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);

    setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);

    setOperationAction(ISD::MUL, MVT::i64, Legal);

    setOperationAction(ISD::MULHS, MVT::i64, Legal);

    setOperationAction(ISD::MULHU, MVT::i64, Legal);

llvm/test/CodeGen/Mips/llvm-ir/add.ll

+30 −0
Original line number Diff line number Diff line
@@ -81,3 +81,33 @@ entry: 
  %r = add i64 %a, %b

  ret i64 %r

}



define signext i128 @add_i128(i128 signext %a, i128 signext %b) {

entry:

; ALL-LABEL: add_i128:



  ; GP32:       lw        $[[T0:[0-9]+]], 28($sp)

  ; GP32:       addu      $[[T1:[0-9]+]], $7, $[[T0]]

  ; GP32:       sltu      $[[T2:[0-9]+]], $[[T1]], $[[T0]]

  ; GP32:       lw        $[[T3:[0-9]+]], 24($sp)

  ; GP32:       addu      $[[T4:[0-9]+]], $[[T2]], $[[T3]]

  ; GP32:       addu      $[[T5:[0-9]+]], $6, $[[T4]]

  ; GP32:       sltu      $[[T6:[0-9]+]], $[[T5]], $[[T3]]

  ; GP32:       lw        $[[T7:[0-9]+]], 20($sp)

  ; GP32:       addu      $[[T8:[0-9]+]], $[[T6]], $[[T7]]

  ; GP32:       lw        $[[T9:[0-9]+]], 16($sp)

  ; GP32:       addu      $3, $5, $[[T8]]

  ; GP32:       sltu      $[[T10:[0-9]+]], $3, $[[T7]]

  ; GP32:       addu      $[[T11:[0-9]+]], $[[T10]], $[[T9]]

  ; GP32:       addu      $2, $4, $[[T11]]

  ; GP32:       move      $4, $[[T5]]

  ; GP32:       move      $5, $[[T1]]



  ; GP64:       daddu     $3, $5, $7

  ; GP64:       sltu      $[[T0:[0-9]+]], $3, $7

  ; GP64:       daddu     $[[T1:[0-9]+]], $[[T0]], $6

  ; GP64:       daddu     $2, $4, $[[T1]]



  %r = add i128 %a, %b

  ret i128 %r

}