Commit 719f7b1f authored by Hans Wennborg's avatar Hans Wennborg
Browse files

Merging r243294: 

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r243294 | mareko | 2015-07-27 11:16:08 -0700 (Mon, 27 Jul 2015) | 9 lines

AMDGPU: don't match vgpr loads for constant loads

Author: Dave Airlie <airlied@redhat.com>

In order to implement indirect sampler loads, we don't
want to match on a VGPR load but an SGPR one for constants,
as we cannot feed VGPRs to the sampler only SGPRs.

this should be applicable for llvm 3.7 as well.
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llvm-svn: 243317
parent 79dde6d4

llvm/lib/Target/AMDGPU/SIInstructions.td

+0 −3
Original line number Diff line number Diff line
@@ -2910,9 +2910,6 @@ defm : MUBUFLoad_Pattern <BUFFER_LOAD_SBYTE_ADDR64, i32, sextloadi8_constant>; 
defm : MUBUFLoad_Pattern <BUFFER_LOAD_UBYTE_ADDR64, i32, az_extloadi8_constant>;

defm : MUBUFLoad_Pattern <BUFFER_LOAD_SSHORT_ADDR64, i32, sextloadi16_constant>;

defm : MUBUFLoad_Pattern <BUFFER_LOAD_USHORT_ADDR64, i32, az_extloadi16_constant>;

defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORD_ADDR64, i32, constant_load>;

defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX2_ADDR64, v2i32, constant_load>;

defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX4_ADDR64, v4i32, constant_load>;

} // End Predicates = [isSICI]



class MUBUFScratchLoadPat <MUBUF Instr, ValueType vt, PatFrag ld> : Pat <

llvm/test/CodeGen/AMDGPU/gv-const-addrspace.ll

+3 −9
Original line number Diff line number Diff line
@@ -8,9 +8,7 @@ 
@float_gv = internal unnamed_addr addrspace(2) constant [5 x float] [float 0.0, float 1.0, float 2.0, float 3.0, float 4.0], align 4



; FUNC-LABEL: {{^}}float:

; FIXME: We should be using s_load_dword here.

; SI: buffer_load_dword

; VI: s_load_dword

; GCN: s_load_dword



; EG-DAG: MOV {{\** *}}T2.X

; EG-DAG: MOV {{\** *}}T3.X
@@ -31,9 +29,7 @@ entry: 


; FUNC-LABEL: {{^}}i32:



; FIXME: We should be using s_load_dword here.

; SI: buffer_load_dword

; VI: s_load_dword

; GCN: s_load_dword



; EG-DAG: MOV {{\** *}}T2.X

; EG-DAG: MOV {{\** *}}T3.X
@@ -71,9 +67,7 @@ define void @struct_foo_gv_load(i32 addrspace(1)* %out, i32 %index) { 
                                                                <1 x i32> <i32 4> ]



; FUNC-LABEL: {{^}}array_v1_gv_load:

; FIXME: We should be using s_load_dword here.

; SI: buffer_load_dword

; VI: s_load_dword

; GCN: s_load_dword

define void @array_v1_gv_load(<1 x i32> addrspace(1)* %out, i32 %index) {

  %gep = getelementptr inbounds [4 x <1 x i32>], [4 x <1 x i32>] addrspace(2)* @array_v1_gv, i32 0, i32 %index

  %load = load <1 x i32>, <1 x i32> addrspace(2)* %gep, align 4

llvm/test/CodeGen/AMDGPU/smrd.ll

+1 −7
Original line number Diff line number Diff line
@@ -43,13 +43,7 @@ entry: 
; GCN-LABEL: {{^}}smrd3:

; FIXME: There are too many copies here because we don't fold immediates

;        through REG_SEQUENCE

; SI: s_mov_b32 s[[SLO:[0-9]+]], 0 ;

; SI: s_mov_b32 s[[SHI:[0-9]+]], 4

; SI: s_mov_b32 s[[SSLO:[0-9]+]], s[[SLO]]

; SI-DAG: v_mov_b32_e32 v[[VLO:[0-9]+]], s[[SSLO]]

; SI-DAG: v_mov_b32_e32 v[[VHI:[0-9]+]], s[[SHI]]

; FIXME: We should be able to use s_load_dword here

; SI: buffer_load_dword v{{[0-9]+}}, v{{\[}}[[VLO]]:[[VHI]]{{\]}}, s[{{[0-9]+:[0-9]+}}], 0 addr64

; SI: s_load_dwordx2 s[{{[0-9]:[0-9]}}], s[{{[0-9]:[0-9]}}], 0xb ; encoding: [0x0b

; TODO: Add VI checks

; GCN: s_endpgm

define void @smrd3(i32 addrspace(1)* %out, i32 addrspace(2)* %ptr) {