Loading llvm/test/CodeGen/AArch64/veclib-llvm.pow.ll +1 −1 Original line number Diff line number Diff line ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 ; RUN: llc -start-before=codegenprepare -mtriple=aarch64-gnu-linux -mattr=+neon,+sve \ ; RUN: llc -mtriple=aarch64-gnu-linux -mattr=+neon,+sve \ ; RUN: -vector-library=ArmPL < %s | FileCheck %s -check-prefix=ARMPL define <4 x float> @test_pow_v4f32(<4 x float> %x, <4 x float> %y) nounwind { Loading Loading
llvm/test/CodeGen/AArch64/veclib-llvm.pow.ll +1 −1 Original line number Diff line number Diff line ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 ; RUN: llc -start-before=codegenprepare -mtriple=aarch64-gnu-linux -mattr=+neon,+sve \ ; RUN: llc -mtriple=aarch64-gnu-linux -mattr=+neon,+sve \ ; RUN: -vector-library=ArmPL < %s | FileCheck %s -check-prefix=ARMPL define <4 x float> @test_pow_v4f32(<4 x float> %x, <4 x float> %y) nounwind { Loading
