Revert "AMDGPU: Cleanup and fix SMRD offset handling" (6a4acb9d) · Commits · llvm-doe / llvm-project

llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp

+14 −19

Original line number	Diff line number	Diff line
		@@ -1771,31 +1771,26 @@ bool AMDGPUDAGToDAGISel::SelectSMRDOffset(SDValue ByteOffsetNode,

		SDLoc SL(ByteOffsetNode);
		GCNSubtarget::Generation Gen = Subtarget->getGeneration();
		uint64_t ByteOffset = C->getZExtValue();
		Optional<int64_t> EncodedOffset =
		AMDGPU::getSMRDEncodedOffset(*Subtarget, ByteOffset);
		if (EncodedOffset) {
		Offset = CurDAG->getTargetConstant(*EncodedOffset, SL, MVT::i32);
		int64_t ByteOffset = C->getSExtValue();
		int64_t EncodedOffset = AMDGPU::getSMRDEncodedOffset(*Subtarget, ByteOffset);

		if (AMDGPU::isLegalSMRDImmOffset(*Subtarget, ByteOffset)) {
		Offset = CurDAG->getTargetConstant(EncodedOffset, SL, MVT::i32);
		Imm = true;
		return true;
		}

		if (Gen == AMDGPUSubtarget::SEA_ISLANDS) {
		EncodedOffset =
		AMDGPU::getSMRDEncodedLiteralOffset32(*Subtarget, ByteOffset);
		if (EncodedOffset) {
		Offset = CurDAG->getTargetConstant(*EncodedOffset, SL, MVT::i32);
		return true;
		}
		}

		if (!isUInt<32>(ByteOffset) && !isInt<32>(ByteOffset))
		if (!isUInt<32>(EncodedOffset) \|\| !isUInt<32>(ByteOffset))
		return false;

		if (Gen == AMDGPUSubtarget::SEA_ISLANDS && isUInt<32>(EncodedOffset)) {
		// 32-bit Immediates are supported on Sea Islands.
		Offset = CurDAG->getTargetConstant(EncodedOffset, SL, MVT::i32);
		} else {
		SDValue C32Bit = CurDAG->getTargetConstant(ByteOffset, SL, MVT::i32);
		Offset = SDValue(
		CurDAG->getMachineNode(AMDGPU::S_MOV_B32, SL, MVT::i32, C32Bit), 0);

		Offset = SDValue(CurDAG->getMachineNode(AMDGPU::S_MOV_B32, SL, MVT::i32,
		C32Bit), 0);
		}
		Imm = false;
		return true;
		}

llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

+7 −7

Original line number	Diff line number	Diff line
		@@ -2107,14 +2107,15 @@ AMDGPUInstructionSelector::selectSmrdImm(MachineOperand &Root) const {
		return None;

		const GEPInfo &GEPInfo = AddrInfo[0];
		Optional<int64_t> EncodedImm = AMDGPU::getSMRDEncodedOffset(STI, GEPInfo.Imm);
		if (!EncodedImm)

		if (!AMDGPU::isLegalSMRDImmOffset(STI, GEPInfo.Imm))
		return None;

		unsigned PtrReg = GEPInfo.SgprParts[0];
		int64_t EncodedImm = AMDGPU::getSMRDEncodedOffset(STI, GEPInfo.Imm);
		return {{
		[=](MachineInstrBuilder &MIB) { MIB.addReg(PtrReg); },
		[=](MachineInstrBuilder &MIB) { MIB.addImm(*EncodedImm); }
		[=](MachineInstrBuilder &MIB) { MIB.addImm(EncodedImm); }
		}};
		}

		@@ -2128,14 +2129,13 @@ AMDGPUInstructionSelector::selectSmrdImm32(MachineOperand &Root) const {

		const GEPInfo &GEPInfo = AddrInfo[0];
		unsigned PtrReg = GEPInfo.SgprParts[0];
		Optional<int64_t> EncodedImm =
		AMDGPU::getSMRDEncodedLiteralOffset32(STI, GEPInfo.Imm);
		if (!EncodedImm)
		int64_t EncodedImm = AMDGPU::getSMRDEncodedOffset(STI, GEPInfo.Imm);
		if (!isUInt<32>(EncodedImm))
		return None;

		return {{
		[=](MachineInstrBuilder &MIB) { MIB.addReg(PtrReg); },
		[=](MachineInstrBuilder &MIB) { MIB.addImm(*EncodedImm); }
		[=](MachineInstrBuilder &MIB) { MIB.addImm(EncodedImm); }
		}};
		}

llvm/lib/Target/AMDGPU/SIFrameLowering.cpp

+1 −1

Original line number	Diff line number	Diff line
		@@ -587,7 +587,7 @@ void SIFrameLowering::emitEntryFunctionScratchSetup(const GCNSubtarget &ST,
		16, 4);
		unsigned Offset = Fn.getCallingConv() == CallingConv::AMDGPU_CS ? 16 : 0;
		const GCNSubtarget &Subtarget = MF.getSubtarget<GCNSubtarget>();
		unsigned EncodedOffset = AMDGPU::convertSMRDOffsetUnits(Subtarget, Offset);
		unsigned EncodedOffset = AMDGPU::getSMRDEncodedOffset(Subtarget, Offset);
		BuildMI(MBB, I, DL, LoadDwordX4, ScratchRsrcReg)
		.addReg(Rsrc01)
		.addImm(EncodedOffset) // offset

llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp

+1 −1

Original line number	Diff line number	Diff line
		@@ -501,7 +501,7 @@ void SILoadStoreOptimizer::CombineInfo::setMI(MachineBasicBlock::iterator MI,
		: 4;
		break;
		case S_BUFFER_LOAD_IMM:
		EltSize = AMDGPU::convertSMRDOffsetUnits(STM, 4);
		EltSize = AMDGPU::getSMRDEncodedOffset(STM, 4);
		break;
		default:
		EltSize = 4;

llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

+5 −32

Original line number	Diff line number	Diff line
		@@ -1247,43 +1247,16 @@ static bool hasSMEMByteOffset(const MCSubtargetInfo &ST) {
		return isGCN3Encoding(ST) \|\| isGFX10(ST);
		}

		static bool isLegalSMRDEncodedImmOffset(const MCSubtargetInfo &ST,
		int64_t EncodedOffset) {
		return hasSMEMByteOffset(ST) ? isUInt<20>(EncodedOffset)
		: isUInt<8>(EncodedOffset);
		}

		static bool isDwordAligned(uint64_t ByteOffset) {
		return (ByteOffset & 3) == 0;
		}

		uint64_t convertSMRDOffsetUnits(const MCSubtargetInfo &ST,
		uint64_t ByteOffset) {
		int64_t getSMRDEncodedOffset(const MCSubtargetInfo &ST, int64_t ByteOffset) {
		if (hasSMEMByteOffset(ST))
		return ByteOffset;

		assert(isDwordAligned(ByteOffset));
		return ByteOffset >> 2;
		}

		Optional<int64_t> getSMRDEncodedOffset(const MCSubtargetInfo &ST,
		int64_t ByteOffset) {
		if (!isDwordAligned(ByteOffset) && !hasSMEMByteOffset(ST))
		return None;

		int64_t EncodedOffset = convertSMRDOffsetUnits(ST, ByteOffset);
		return isLegalSMRDEncodedImmOffset(ST, EncodedOffset) ?
		Optional<int64_t>(EncodedOffset) : None;
		}

		Optional<int64_t> getSMRDEncodedLiteralOffset32(const MCSubtargetInfo &ST,
		int64_t ByteOffset) {
		if (!isDwordAligned(ByteOffset) && !hasSMEMByteOffset(ST))
		return None;

		assert(isCI(ST));
		int64_t EncodedOffset = convertSMRDOffsetUnits(ST, ByteOffset);
		return isUInt<32>(EncodedOffset) ? Optional<int64_t>(EncodedOffset) : None;
		bool isLegalSMRDImmOffset(const MCSubtargetInfo &ST, int64_t ByteOffset) {
		int64_t EncodedOffset = getSMRDEncodedOffset(ST, ByteOffset);
		return (hasSMEMByteOffset(ST)) ?
		isUInt<20>(EncodedOffset) : isUInt<8>(EncodedOffset);
		}

		// Given Imm, split it into the values to put into the SOffset and ImmOffset