Commit 69b3f16a authored by Hans Wennborg's avatar Hans Wennborg
Browse files

Merging r324110: 

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r324110 | aemerson | 2018-02-02 19:03:30 +0100 (Fri, 02 Feb 2018) | 3 lines

[AArch64][GlobalISel] Use getRegClassForTypeOnBank() in selectCopy.

Differential Revision: https://reviews.llvm.org/D42832
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llvm-svn: 325584
parent 5f967a72

llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp

+15 −23
Original line number Diff line number Diff line
@@ -133,16 +133,21 @@ AArch64InstructionSelector::AArch64InstructionSelector( 
// for each class in the bank.

static const TargetRegisterClass *

getRegClassForTypeOnBank(LLT Ty, const RegisterBank &RB,

                         const RegisterBankInfo &RBI) {

                         const RegisterBankInfo &RBI,

                         bool GetAllRegSet = false) {

  if (RB.getID() == AArch64::GPRRegBankID) {

    if (Ty.getSizeInBits() <= 32)

      return &AArch64::GPR32RegClass;

      return GetAllRegSet ? &AArch64::GPR32allRegClass

                          : &AArch64::GPR32RegClass;

    if (Ty.getSizeInBits() == 64)

      return &AArch64::GPR64RegClass;

      return GetAllRegSet ? &AArch64::GPR64allRegClass

                          : &AArch64::GPR64RegClass;

    return nullptr;

  }



  if (RB.getID() == AArch64::FPRRegBankID) {

    if (Ty.getSizeInBits() <= 16)

      return &AArch64::FPR16RegClass;

    if (Ty.getSizeInBits() == 32)

      return &AArch64::FPR32RegClass;

    if (Ty.getSizeInBits() == 64)
@@ -322,6 +327,7 @@ static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII, 


  const RegisterBank &RegBank = *RBI.getRegBank(DstReg, MRI, TRI);

  const unsigned DstSize = MRI.getType(DstReg).getSizeInBits();

  (void)DstSize;

  unsigned SrcReg = I.getOperand(1).getReg();

  const unsigned SrcSize = RBI.getSizeInBits(SrcReg, MRI, TRI);

  (void)SrcSize;
@@ -340,27 +346,13 @@ static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII, 
      "Copy with different width?!");

  assert((DstSize <= 64 || RegBank.getID() == AArch64::FPRRegBankID) &&

         "GPRs cannot get more than 64-bit width values");

  const TargetRegisterClass *RC = nullptr;



  if (RegBank.getID() == AArch64::FPRRegBankID) {

    if (DstSize <= 16)

      RC = &AArch64::FPR16RegClass;

    else if (DstSize <= 32)

      RC = &AArch64::FPR32RegClass;

    else if (DstSize <= 64)

      RC = &AArch64::FPR64RegClass;

    else if (DstSize <= 128)

      RC = &AArch64::FPR128RegClass;

    else {



  const TargetRegisterClass *RC = getRegClassForTypeOnBank(

      MRI.getType(DstReg), RegBank, RBI, /* GetAllRegSet */ true);

  if (!RC) {

    DEBUG(dbgs() << "Unexpected bitcast size " << DstSize << '\n');

    return false;

  }

  } else {

    assert(RegBank.getID() == AArch64::GPRRegBankID &&

           "Bitcast for the flags?");

    RC =

        DstSize <= 32 ? &AArch64::GPR32allRegClass : &AArch64::GPR64allRegClass;

  }



  // No need to constrain SrcReg. It will get constrained when

  // we hit another of its use or its defs.