Commit 67a87753 authored by Amara Emerson's avatar Amara Emerson
Browse files

[AArch64] Don't generate gpr CSEL instructions in early-ifcvt if regclasses aren't compatible. 

In GlobalISel we may in some unfortunate circumstances generate PHIs with
operands that are on separate banks. If-conversion doesn't currently check for
that case and ends up generating a CSEL on AArch64 with incorrect register
operands.

Differential Revision: https://reviews.llvm.org/D72961
parent 5fdad8e3

llvm/include/llvm/CodeGen/TargetInstrInfo.h

+5 −3
Original line number Diff line number Diff line
@@ -838,15 +838,17 @@ public: 
  ///

  /// @param MBB         Block where select instruction would be inserted.

  /// @param Cond        Condition returned by analyzeBranch.

  /// @param DstReg      Virtual dest register that the result should write to.

  /// @param TrueReg     Virtual register to select when Cond is true.

  /// @param FalseReg    Virtual register to select when Cond is false.

  /// @param CondCycles  Latency from Cond+Branch to select output.

  /// @param TrueCycles  Latency from TrueReg to select output.

  /// @param FalseCycles Latency from FalseReg to select output.

  virtual bool canInsertSelect(const MachineBasicBlock &MBB,

                               ArrayRef<MachineOperand> Cond, unsigned TrueReg,

                               unsigned FalseReg, int &CondCycles,

                               int &TrueCycles, int &FalseCycles) const {

                               ArrayRef<MachineOperand> Cond, unsigned DstReg,

                               unsigned TrueReg, unsigned FalseReg,

                               int &CondCycles, int &TrueCycles,

                               int &FalseCycles) const {

    return false;

  }

llvm/lib/CodeGen/EarlyIfConversion.cpp

+3 −2
Original line number Diff line number Diff line
@@ -520,8 +520,9 @@ bool SSAIfConv::canConvertIf(MachineBasicBlock *MBB, bool Predicate) { 
    assert(Register::isVirtualRegister(PI.FReg) && "Bad PHI");



    // Get target information.

    if (!TII->canInsertSelect(*Head, Cond, PI.TReg, PI.FReg,

                              PI.CondCycles, PI.TCycles, PI.FCycles)) {

    if (!TII->canInsertSelect(*Head, Cond, PI.PHI->getOperand(0).getReg(),

                              PI.TReg, PI.FReg, PI.CondCycles, PI.TCycles,

                              PI.FCycles)) {

      LLVM_DEBUG(dbgs() << "Can't convert: " << *PI.PHI);

      return false;

    }

llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

+9 −2
Original line number Diff line number Diff line
@@ -496,8 +496,9 @@ static unsigned canFoldIntoCSel(const MachineRegisterInfo &MRI, unsigned VReg, 


bool AArch64InstrInfo::canInsertSelect(const MachineBasicBlock &MBB,

                                       ArrayRef<MachineOperand> Cond,

                                       unsigned TrueReg, unsigned FalseReg,

                                       int &CondCycles, int &TrueCycles,

                                       unsigned DstReg, unsigned TrueReg,

                                       unsigned FalseReg, int &CondCycles,

                                       int &TrueCycles,

                                       int &FalseCycles) const {

  // Check register classes.

  const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
@@ -506,6 +507,12 @@ bool AArch64InstrInfo::canInsertSelect(const MachineBasicBlock &MBB, 
  if (!RC)

    return false;



  // Also need to check the dest regclass, in case we're trying to optimize

  // something like:

  // %1(gpr) = PHI %2(fpr), bb1, %(fpr), bb2

  if (!RI.getCommonSubClass(RC, MRI.getRegClass(DstReg)))

    return false;



  // Expanding cbz/tbz requires an extra cycle of latency on the condition.

  unsigned ExtraCondLat = Cond.size() != 1;

llvm/lib/Target/AArch64/AArch64InstrInfo.h

+2 −1
Original line number Diff line number Diff line
@@ -191,7 +191,8 @@ public: 
  bool

  reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;

  bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond,

                       unsigned, unsigned, int &, int &, int &) const override;

                       unsigned, unsigned, unsigned, int &, int &,

                       int &) const override;

  void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,

                    const DebugLoc &DL, unsigned DstReg,

                    ArrayRef<MachineOperand> Cond, unsigned TrueReg,

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

+2 −2
Original line number Diff line number Diff line
@@ -2128,8 +2128,8 @@ bool SIInstrInfo::reverseBranchCondition( 


bool SIInstrInfo::canInsertSelect(const MachineBasicBlock &MBB,

                                  ArrayRef<MachineOperand> Cond,

                                  unsigned TrueReg, unsigned FalseReg,

                                  int &CondCycles,

                                  unsigned DstReg, unsigned TrueReg,

                                  unsigned FalseReg, int &CondCycles,

                                  int &TrueCycles, int &FalseCycles) const {

  switch (Cond[0].getImm()) {

  case VCCNZ: