Commit 66069363 authored by Craig Topper's avatar Craig Topper
Browse files

[RISCV] Remove -target-abi from half-bitmanip-dagcombines.ll. 

This should be testing the custom ISD nodes we use for passing
half values in GPRs.

We should optimize these to integer operations, but we currently
don't.
parent 88bc29f5

llvm/test/CodeGen/RISCV/half-bitmanip-dagcombines.ll

+22 −10
Original line number Diff line number Diff line
@@ -2,13 +2,11 @@ 
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \

; RUN:   | FileCheck -check-prefix=RV32I %s

; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfh -verify-machineinstrs \

; RUN:   -target-abi ilp32f < %s \

; RUN:   | FileCheck -check-prefix=RV32IZFH %s

; RUN:   < %s | FileCheck -check-prefix=RV32IZFH %s

; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \

; RUN:   | FileCheck -check-prefix=RV64I %s

; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfh -verify-machineinstrs \

; RUN:   -target-abi lp64f < %s \

; RUN:   | FileCheck -check-prefix=RV64IZFH %s

; RUN:   < %s | FileCheck -check-prefix=RV64IZFH %s



; This file tests cases where simple floating point operations can be

; profitably handled though bit manipulation if a soft-float ABI is being used
@@ -25,7 +23,9 @@ define half @fneg(half %a) nounwind { 
;

; RV32IZFH-LABEL: fneg:

; RV32IZFH:       # %bb.0:

; RV32IZFH-NEXT:    fneg.h fa0, fa0

; RV32IZFH-NEXT:    fmv.h.x ft0, a0

; RV32IZFH-NEXT:    fneg.h ft0, ft0

; RV32IZFH-NEXT:    fmv.x.h a0, ft0

; RV32IZFH-NEXT:    ret

;

; RV64I-LABEL: fneg:
@@ -36,7 +36,9 @@ define half @fneg(half %a) nounwind { 
;

; RV64IZFH-LABEL: fneg:

; RV64IZFH:       # %bb.0:

; RV64IZFH-NEXT:    fneg.h fa0, fa0

; RV64IZFH-NEXT:    fmv.h.x ft0, a0

; RV64IZFH-NEXT:    fneg.h ft0, ft0

; RV64IZFH-NEXT:    fmv.x.h a0, ft0

; RV64IZFH-NEXT:    ret

  %1 = fneg half %a

  ret half %1
@@ -54,7 +56,9 @@ define half @fabs(half %a) nounwind { 
;

; RV32IZFH-LABEL: fabs:

; RV32IZFH:       # %bb.0:

; RV32IZFH-NEXT:    fabs.h fa0, fa0

; RV32IZFH-NEXT:    fmv.h.x ft0, a0

; RV32IZFH-NEXT:    fabs.h ft0, ft0

; RV32IZFH-NEXT:    fmv.x.h a0, ft0

; RV32IZFH-NEXT:    ret

;

; RV64I-LABEL: fabs:
@@ -66,7 +70,9 @@ define half @fabs(half %a) nounwind { 
;

; RV64IZFH-LABEL: fabs:

; RV64IZFH:       # %bb.0:

; RV64IZFH-NEXT:    fabs.h fa0, fa0

; RV64IZFH-NEXT:    fmv.h.x ft0, a0

; RV64IZFH-NEXT:    fabs.h ft0, ft0

; RV64IZFH-NEXT:    fmv.x.h a0, ft0

; RV64IZFH-NEXT:    ret

  %1 = call half @llvm.fabs.f16(half %a)

  ret half %1
@@ -92,7 +98,10 @@ define half @fcopysign_fneg(half %a, half %b) nounwind { 
;

; RV32IZFH-LABEL: fcopysign_fneg:

; RV32IZFH:       # %bb.0:

; RV32IZFH-NEXT:    fsgnjn.h fa0, fa0, fa1

; RV32IZFH-NEXT:    fmv.h.x ft0, a1

; RV32IZFH-NEXT:    fmv.h.x ft1, a0

; RV32IZFH-NEXT:    fsgnjn.h ft0, ft1, ft0

; RV32IZFH-NEXT:    fmv.x.h a0, ft0

; RV32IZFH-NEXT:    ret

;

; RV64I-LABEL: fcopysign_fneg:
@@ -108,7 +117,10 @@ define half @fcopysign_fneg(half %a, half %b) nounwind { 
;

; RV64IZFH-LABEL: fcopysign_fneg:

; RV64IZFH:       # %bb.0:

; RV64IZFH-NEXT:    fsgnjn.h fa0, fa0, fa1

; RV64IZFH-NEXT:    fmv.h.x ft0, a1

; RV64IZFH-NEXT:    fmv.h.x ft1, a0

; RV64IZFH-NEXT:    fsgnjn.h ft0, ft1, ft0

; RV64IZFH-NEXT:    fmv.x.h a0, ft0

; RV64IZFH-NEXT:    ret

  %1 = fneg half %b

  %2 = call half @llvm.copysign.f16(half %a, half %1)