Loading llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp +7 −7 Original line number Diff line number Diff line Loading @@ -197,15 +197,15 @@ AMDGPURegisterBankInfo::AMDGPURegisterBankInfo(const GCNSubtarget &ST) TII(Subtarget.getInstrInfo()) { // HACK: Until this is fully tablegen'd. static bool AlreadyInit = false; if (AlreadyInit) return; AlreadyInit = true; static llvm::once_flag InitializeRegisterBankFlag; static auto InitializeRegisterBankOnce = [this]() { assert(&getRegBank(AMDGPU::SGPRRegBankID) == &AMDGPU::SGPRRegBank && &getRegBank(AMDGPU::VGPRRegBankID) == &AMDGPU::VGPRRegBank && &getRegBank(AMDGPU::AGPRRegBankID) == &AMDGPU::AGPRRegBank); }; llvm::call_once(InitializeRegisterBankFlag, InitializeRegisterBankOnce); } static bool isVectorRegisterBank(const RegisterBank &Bank) { Loading Loading
llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp +7 −7 Original line number Diff line number Diff line Loading @@ -197,15 +197,15 @@ AMDGPURegisterBankInfo::AMDGPURegisterBankInfo(const GCNSubtarget &ST) TII(Subtarget.getInstrInfo()) { // HACK: Until this is fully tablegen'd. static bool AlreadyInit = false; if (AlreadyInit) return; AlreadyInit = true; static llvm::once_flag InitializeRegisterBankFlag; static auto InitializeRegisterBankOnce = [this]() { assert(&getRegBank(AMDGPU::SGPRRegBankID) == &AMDGPU::SGPRRegBank && &getRegBank(AMDGPU::VGPRRegBankID) == &AMDGPU::VGPRRegBank && &getRegBank(AMDGPU::AGPRRegBankID) == &AMDGPU::AGPRRegBank); }; llvm::call_once(InitializeRegisterBankFlag, InitializeRegisterBankOnce); } static bool isVectorRegisterBank(const RegisterBank &Bank) { Loading