Commit 62217670 authored by Matt Arsenault's avatar Matt Arsenault Committed by Matt Arsenault
Browse files

DAG: Add DAG argument to isFPExtFoldable 

For AMDGPU this is dependent on the FP mode, which should eventually
not be a property of the subtarget.
parent a07019a2

llvm/include/llvm/CodeGen/TargetLowering.h

+2 −1
Original line number Diff line number Diff line
@@ -2491,7 +2491,8 @@ public: 
  /// Return true if an fpext operation input to an \p Opcode operation is free

  /// (for instance, because half-precision floating-point numbers are

  /// implicitly extended to float-precision) for an FMA instruction.

  virtual bool isFPExtFoldable(unsigned Opcode, EVT DestVT, EVT SrcVT) const {

  virtual bool isFPExtFoldable(const SelectionDAG &DAG, unsigned Opcode,

                               EVT DestVT, EVT SrcVT) const {

    assert(DestVT.isFloatingPoint() && SrcVT.isFloatingPoint() &&

           "invalid fpext types");

    return isFPExtFree(DestVT, SrcVT);

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

+28 −14
Original line number Diff line number Diff line
@@ -11390,7 +11390,8 @@ SDValue DAGCombiner::visitFADDForFMACombine(SDNode *N) { 
  if (N0.getOpcode() == ISD::FP_EXTEND) {

    SDValue N00 = N0.getOperand(0);

    if (isContractableFMUL(N00) &&

        TLI.isFPExtFoldable(PreferredFusedOpcode, VT, N00.getValueType())) {

        TLI.isFPExtFoldable(DAG, PreferredFusedOpcode, VT,

                            N00.getValueType())) {

      return DAG.getNode(PreferredFusedOpcode, SL, VT,

                         DAG.getNode(ISD::FP_EXTEND, SL, VT,

                                     N00.getOperand(0)),
@@ -11404,7 +11405,8 @@ SDValue DAGCombiner::visitFADDForFMACombine(SDNode *N) { 
  if (N1.getOpcode() == ISD::FP_EXTEND) {

    SDValue N10 = N1.getOperand(0);

    if (isContractableFMUL(N10) &&

        TLI.isFPExtFoldable(PreferredFusedOpcode, VT, N10.getValueType())) {

        TLI.isFPExtFoldable(DAG, PreferredFusedOpcode, VT,

                            N10.getValueType())) {

      return DAG.getNode(PreferredFusedOpcode, SL, VT,

                         DAG.getNode(ISD::FP_EXTEND, SL, VT,

                                     N10.getOperand(0)),
@@ -11458,7 +11460,8 @@ SDValue DAGCombiner::visitFADDForFMACombine(SDNode *N) { 
      if (N02.getOpcode() == ISD::FP_EXTEND) {

        SDValue N020 = N02.getOperand(0);

        if (isContractableFMUL(N020) &&

            TLI.isFPExtFoldable(PreferredFusedOpcode, VT, N020.getValueType())) {

            TLI.isFPExtFoldable(DAG, PreferredFusedOpcode, VT,

                                N020.getValueType())) {

          return FoldFAddFMAFPExtFMul(N0.getOperand(0), N0.getOperand(1),

                                      N020.getOperand(0), N020.getOperand(1),

                                      N1, Flags);
@@ -11487,7 +11490,8 @@ SDValue DAGCombiner::visitFADDForFMACombine(SDNode *N) { 
      if (N00.getOpcode() == PreferredFusedOpcode) {

        SDValue N002 = N00.getOperand(2);

        if (isContractableFMUL(N002) &&

            TLI.isFPExtFoldable(PreferredFusedOpcode, VT, N00.getValueType())) {

            TLI.isFPExtFoldable(DAG, PreferredFusedOpcode, VT,

                                N00.getValueType())) {

          return FoldFAddFPExtFMAFMul(N00.getOperand(0), N00.getOperand(1),

                                      N002.getOperand(0), N002.getOperand(1),

                                      N1, Flags);
@@ -11502,7 +11506,8 @@ SDValue DAGCombiner::visitFADDForFMACombine(SDNode *N) { 
      if (N12.getOpcode() == ISD::FP_EXTEND) {

        SDValue N120 = N12.getOperand(0);

        if (isContractableFMUL(N120) &&

            TLI.isFPExtFoldable(PreferredFusedOpcode, VT, N120.getValueType())) {

            TLI.isFPExtFoldable(DAG, PreferredFusedOpcode, VT,

                                N120.getValueType())) {

          return FoldFAddFMAFPExtFMul(N1.getOperand(0), N1.getOperand(1),

                                      N120.getOperand(0), N120.getOperand(1),

                                      N0, Flags);
@@ -11520,7 +11525,8 @@ SDValue DAGCombiner::visitFADDForFMACombine(SDNode *N) { 
      if (N10.getOpcode() == PreferredFusedOpcode) {

        SDValue N102 = N10.getOperand(2);

        if (isContractableFMUL(N102) &&

            TLI.isFPExtFoldable(PreferredFusedOpcode, VT, N10.getValueType())) {

            TLI.isFPExtFoldable(DAG, PreferredFusedOpcode, VT,

                                N10.getValueType())) {

          return FoldFAddFPExtFMAFMul(N10.getOperand(0), N10.getOperand(1),

                                      N102.getOperand(0), N102.getOperand(1),

                                      N0, Flags);
@@ -11610,7 +11616,8 @@ SDValue DAGCombiner::visitFSUBForFMACombine(SDNode *N) { 
  if (N0.getOpcode() == ISD::FP_EXTEND) {

    SDValue N00 = N0.getOperand(0);

    if (isContractableFMUL(N00) &&

        TLI.isFPExtFoldable(PreferredFusedOpcode, VT, N00.getValueType())) {

        TLI.isFPExtFoldable(DAG, PreferredFusedOpcode, VT,

                            N00.getValueType())) {

      return DAG.getNode(PreferredFusedOpcode, SL, VT,

                         DAG.getNode(ISD::FP_EXTEND, SL, VT,

                                     N00.getOperand(0)),
@@ -11626,7 +11633,8 @@ SDValue DAGCombiner::visitFSUBForFMACombine(SDNode *N) { 
  if (N1.getOpcode() == ISD::FP_EXTEND) {

    SDValue N10 = N1.getOperand(0);

    if (isContractableFMUL(N10) &&

        TLI.isFPExtFoldable(PreferredFusedOpcode, VT, N10.getValueType())) {

        TLI.isFPExtFoldable(DAG, PreferredFusedOpcode, VT,

                            N10.getValueType())) {

      return DAG.getNode(PreferredFusedOpcode, SL, VT,

                         DAG.getNode(ISD::FNEG, SL, VT,

                                     DAG.getNode(ISD::FP_EXTEND, SL, VT,
@@ -11648,7 +11656,8 @@ SDValue DAGCombiner::visitFSUBForFMACombine(SDNode *N) { 
    if (N00.getOpcode() == ISD::FNEG) {

      SDValue N000 = N00.getOperand(0);

      if (isContractableFMUL(N000) &&

          TLI.isFPExtFoldable(PreferredFusedOpcode, VT, N00.getValueType())) {

          TLI.isFPExtFoldable(DAG, PreferredFusedOpcode, VT,

                              N00.getValueType())) {

        return DAG.getNode(ISD::FNEG, SL, VT,

                           DAG.getNode(PreferredFusedOpcode, SL, VT,

                                       DAG.getNode(ISD::FP_EXTEND, SL, VT,
@@ -11671,7 +11680,8 @@ SDValue DAGCombiner::visitFSUBForFMACombine(SDNode *N) { 
    if (N00.getOpcode() == ISD::FP_EXTEND) {

      SDValue N000 = N00.getOperand(0);

      if (isContractableFMUL(N000) &&

          TLI.isFPExtFoldable(PreferredFusedOpcode, VT, N000.getValueType())) {

          TLI.isFPExtFoldable(DAG, PreferredFusedOpcode, VT,

                              N000.getValueType())) {

        return DAG.getNode(ISD::FNEG, SL, VT,

                           DAG.getNode(PreferredFusedOpcode, SL, VT,

                                       DAG.getNode(ISD::FP_EXTEND, SL, VT,
@@ -11722,7 +11732,8 @@ SDValue DAGCombiner::visitFSUBForFMACombine(SDNode *N) { 
      if (N02.getOpcode() == ISD::FP_EXTEND) {

        SDValue N020 = N02.getOperand(0);

        if (isContractableFMUL(N020) &&

            TLI.isFPExtFoldable(PreferredFusedOpcode, VT, N020.getValueType())) {

            TLI.isFPExtFoldable(DAG, PreferredFusedOpcode, VT,

                                N020.getValueType())) {

          return DAG.getNode(PreferredFusedOpcode, SL, VT,

                             N0.getOperand(0), N0.getOperand(1),

                             DAG.getNode(PreferredFusedOpcode, SL, VT,
@@ -11747,7 +11758,8 @@ SDValue DAGCombiner::visitFSUBForFMACombine(SDNode *N) { 
      if (N00.getOpcode() == PreferredFusedOpcode) {

        SDValue N002 = N00.getOperand(2);

        if (isContractableFMUL(N002) &&

            TLI.isFPExtFoldable(PreferredFusedOpcode, VT, N00.getValueType())) {

            TLI.isFPExtFoldable(DAG, PreferredFusedOpcode, VT,

                                N00.getValueType())) {

          return DAG.getNode(PreferredFusedOpcode, SL, VT,

                             DAG.getNode(ISD::FP_EXTEND, SL, VT,

                                         N00.getOperand(0)),
@@ -11770,7 +11782,8 @@ SDValue DAGCombiner::visitFSUBForFMACombine(SDNode *N) { 
        N1.getOperand(2).getOpcode() == ISD::FP_EXTEND) {

      SDValue N120 = N1.getOperand(2).getOperand(0);

      if (isContractableFMUL(N120) &&

          TLI.isFPExtFoldable(PreferredFusedOpcode, VT, N120.getValueType())) {

          TLI.isFPExtFoldable(DAG, PreferredFusedOpcode, VT,

                              N120.getValueType())) {

        SDValue N1200 = N120.getOperand(0);

        SDValue N1201 = N120.getOperand(1);

        return DAG.getNode(PreferredFusedOpcode, SL, VT,
@@ -11799,7 +11812,8 @@ SDValue DAGCombiner::visitFSUBForFMACombine(SDNode *N) { 
      SDValue N101 = CvtSrc.getOperand(1);

      SDValue N102 = CvtSrc.getOperand(2);

      if (isContractableFMUL(N102) &&

          TLI.isFPExtFoldable(PreferredFusedOpcode, VT, CvtSrc.getValueType())) {

          TLI.isFPExtFoldable(DAG, PreferredFusedOpcode, VT,

                              CvtSrc.getValueType())) {

        SDValue N1020 = N102.getOperand(0);

        SDValue N1021 = N102.getOperand(1);

        return DAG.getNode(PreferredFusedOpcode, SL, VT,

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

+2 −2
Original line number Diff line number Diff line
@@ -761,7 +761,7 @@ const GCNSubtarget *SITargetLowering::getSubtarget() const { 
//

// There is only one special case when denormals are enabled we don't currently,

// where this is OK to use.

bool SITargetLowering::isFPExtFoldable(unsigned Opcode,

bool SITargetLowering::isFPExtFoldable(const SelectionDAG &DAG, unsigned Opcode,

                                       EVT DestVT, EVT SrcVT) const {

  return ((Opcode == ISD::FMAD && Subtarget->hasMadMixInsts()) ||

          (Opcode == ISD::FMA && Subtarget->hasFmaMixInsts())) &&

llvm/lib/Target/AMDGPU/SIISelLowering.h

+2 −1
Original line number Diff line number Diff line
@@ -222,7 +222,8 @@ public: 


  const GCNSubtarget *getSubtarget() const;



  bool isFPExtFoldable(unsigned Opcode, EVT DestVT, EVT SrcVT) const override;

  bool isFPExtFoldable(const SelectionDAG &DAG, unsigned Opcode, EVT DestVT,

                       EVT SrcVT) const override;



  bool isShuffleMaskLegal(ArrayRef<int> /*Mask*/, EVT /*VT*/) const override;