Commit 5f15b4e8 authored by Bill Wendling's avatar Bill Wendling
Browse files

Merging r155668: 

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r155668 | atrick | 2012-04-26 14:48:25 -0700 (Thu, 26 Apr 2012) | 8 lines

Fix the SD scheduler to avoid gluing the same node twice.

DAGCombine strangeness may result in multiple loads from the same
offset. They both may try to glue themselves to another load. We could
insist that the redundant loads glue themselves to each other, but the
beter fix is to bail out from bad gluing at the time we detect it.

Fixes rdar://11314175: BuildSchedUnits assert.
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llvm-svn: 155672
parent 988b10e3

llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp

+5 −3
Original line number Diff line number Diff line
@@ -138,9 +138,11 @@ static void AddGlue(SDNode *N, SDValue Glue, bool AddGlue, SelectionDAG *DAG) { 
  // Don't add glue from a node to itself.

  if (GlueDestNode == N) return;



  // Don't add glue to something which already has glue.

  if (N->getValueType(N->getNumValues() - 1) == MVT::Glue) return;



  // Don't add glue to something that already has it, either as a use or value.

  if (N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue ||

      N->getValueType(N->getNumValues() - 1) == MVT::Glue) {

    return;

  }

  for (unsigned I = 0, E = N->getNumValues(); I != E; ++I)

    VTs.push_back(N->getValueType(I));

llvm/test/CodeGen/X86/2012-04-26-sdglue.ll

0 → 100644
+46 −0
Original line number Diff line number Diff line 
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core-avx2 -mattr=+avx | FileCheck %s

; rdar://11314175: SD Scheduler, BuildSchedUnits assert:

;                  N->getNodeId() == -1 && "Node already inserted!



; It's hard to test for the ISEL condition because CodeGen optimizes

; away the bugpointed code. Just ensure the basics are still there.

;CHECK: func:

;CHECK: vmovups

;CHECK: vpshufd

;CHECK: vpshufd

;CHECK: vmulps

;CHECK: vmulps

;CHECK: ret



define void @func() nounwind ssp {

  %tmp = load <4 x float>* null, align 1

  %tmp14 = getelementptr <4 x float>* null, i32 2

  %tmp15 = load <4 x float>* %tmp14, align 1

  %tmp16 = shufflevector <4 x float> %tmp, <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 4, i32 4, i32 4>

  %tmp17 = call <8 x float> @llvm.x86.avx.vinsertf128.ps.256(<8 x float> %tmp16, <4 x float> undef, i8 1)

  %tmp18 = bitcast <4 x float> %tmp to <16 x i8>

  %tmp19 = shufflevector <16 x i8> %tmp18, <16 x i8> undef, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19>

  %tmp20 = bitcast <16 x i8> %tmp19 to <4 x float>

  %tmp21 = bitcast <4 x float> %tmp15 to <16 x i8>

  %tmp22 = shufflevector <16 x i8> undef, <16 x i8> %tmp21, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19>

  %tmp23 = bitcast <16 x i8> %tmp22 to <4 x float>

  %tmp24 = shufflevector <4 x float> %tmp20, <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 4, i32 4, i32 4>

  %tmp25 = call <8 x float> @llvm.x86.avx.vinsertf128.ps.256(<8 x float> %tmp24, <4 x float> %tmp23, i8 1)

  %tmp26 = fmul <8 x float> %tmp17, undef

  %tmp27 = fmul <8 x float> %tmp25, undef

  %tmp28 = fadd <8 x float> %tmp26, %tmp27

  %tmp29 = fadd <8 x float> %tmp28, undef

  %tmp30 = shufflevector <8 x float> %tmp29, <8 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>

  %tmp31 = fmul <4 x float> undef, %tmp30

  %tmp32 = call <8 x float> @llvm.x86.avx.vinsertf128.ps.256(<8 x float> zeroinitializer, <4 x float> %tmp31, i8 1)

  %tmp33 = fadd <8 x float> undef, %tmp32

  %tmp34 = call <8 x float> @llvm.x86.avx.hadd.ps.256(<8 x float> %tmp33, <8 x float> undef) nounwind

  %tmp35 = fsub <8 x float> %tmp34, undef

  %tmp36 = call <8 x float> @llvm.x86.avx.hadd.ps.256(<8 x float> zeroinitializer, <8 x float> %tmp35) nounwind

  store <8 x float> %tmp36, <8 x float>* undef, align 32

  ret void

}



declare <8 x float> @llvm.x86.avx.vinsertf128.ps.256(<8 x float>, <4 x float>, i8) nounwind readnone



declare <8 x float> @llvm.x86.avx.hadd.ps.256(<8 x float>, <8 x float>) nounwind readnone