Commit 5e57f799 authored by Hans Wennborg's avatar Hans Wennborg
Browse files

Merging r243519: 

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r243519 | wschmidt | 2015-07-29 07:31:57 -0700 (Wed, 29 Jul 2015) | 14 lines

[PPC] Fix PR24216: Don't generate splat for misaligned shuffle mask

Given certain shuffle-vector masks, LLVM emits splat instructions
which splat the wrong bytes from the source register.  The issue is
that the function PPC::isSplatShuffleMask() in PPCISelLowering.cpp
does not ensure that the splat pattern found is requesting bytes that
are aligned on an EltSize boundary.  This patch detects this situation
as not a valid splat mask, resulting in a permute being generated
instead of a splat.

Patch and test case by Tyler Kenney, cleaned up a bit by me.

This is a simple bug fix that would be good to incorporate into 3.7.

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llvm-svn: 243528
parent 2b53f11c

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

+5 −0
Original line number Diff line number Diff line
@@ -1430,6 +1430,11 @@ bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) { 
  assert(N->getValueType(0) == MVT::v16i8 &&

         (EltSize == 1 || EltSize == 2 || EltSize == 4));



  // The consecutive indices need to specify an element, not part of two

  // different elements.  So abandon ship early if this isn't the case.

  if (N->getMaskElt(0) % EltSize != 0)

    return false;



  // This is a splat operation if each element of the permute is the same, and

  // if the value doesn't reference the second vector.

  unsigned ElementBase = N->getMaskElt(0);

llvm/test/CodeGen/PowerPC/pr24216.ll

0 → 100644
+14 −0
Original line number Diff line number Diff line 
; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s



; Test case adapted from PR24216.



define void @foo(<16 x i8>* nocapture readonly %in, <16 x i8>* nocapture %out) {

entry:

  %0 = load <16 x i8>, <16 x i8>* %in, align 16

  %1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 2, i32 3, i32 4, i32 5, i32 2, i32 3, i32 4, i32 5, i32 2, i32 3, i32 4, i32 5, i32 2, i32 3, i32 4, i32 5>

  store <16 x i8> %1, <16 x i8>* %out, align 16

  ret void

}



; CHECK: vperm

; CHECK-NOT: vspltw